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A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array

IEEE journal of solid-state circuits, 2018-02, Vol.53 (2), p.642-655

2018

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A Variation-Tolerant In-Memory Machine Learning Classifier via On-Chip Training

IEEE journal of solid-state circuits, 2018-11, Vol.53 (11), p.3163-3173

2018

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High-throughput LDPC decoders

IEEE transactions on very large scale integration (VLSI) systems, 2003-12, Vol.11 (6), p.976-996

2003

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A 640-Mb/s 2048-bit programmable LDPC decoder chip

IEEE journal of solid-state circuits, 2006-03, Vol.41 (3), p.684-698

2006

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An Energy-Efficient ECG Processor in 45-nm CMOS Using Statistical Error Compensation

IEEE journal of solid-state circuits, 2013-11, Vol.48 (11), p.2882-2893

2013

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Development and initial validation of a theory of planned behavior questionnaire: Assessment of purchase intentions towards products associated with CRM campaigns

Cogent business & management, 2023-12, Vol.10 (2), p.1-37

2023

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Enhancing the Accuracy of 6T SRAM-Based In-Memory Architecture via Maximum Likelihood Detection

IEEE transactions on signal processing, 2024, Vol.72, p.2799-2811

2024

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Energy-Accuracy Trade-offs for Resistive In-Memory Computing Architectures

IEEE journal on exploratory solid-state computational devices and circuits, 2024-01, Vol.10, p.1-1

2024

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Litter Quality Affects Termite Sheeting Production and Water Infiltration in the Soil

Behavioral ecology and sociobiology, 2019-11, Vol.66 (3), p.491

2019

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Coding for system-on-chip networks: a unified framework

IEEE transactions on very large scale integration (VLSI) systems, 2005-06, Vol.13 (6), p.655-667

2005

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Error-Resilient Low-Power Viterbi Decoder Architectures

IEEE transactions on signal processing, 2009-12, Vol.57 (12), p.4906-4917

2009

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Soft N-Modular Redundancy

IEEE transactions on computers, 2012-03, Vol.61 (3), p.323-336

2012

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Signal Processing Methods to Enhance the Energy Efficiency of In-Memory Computing Architectures

IEEE transactions on signal processing, 2021, Vol.69, p.6462-6472

2021

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Soft digital signal processing

IEEE transactions on very large scale integration (VLSI) systems, 2001-12, Vol.9 (6), p.813-823

2001

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Deep in-Memory Architectures for Machine Learning

1st ed. 2020., 2020

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Sequential Element Design With Built-In Soft Error Resilience

IEEE transactions on very large scale integration (VLSI) systems, 2006-12, Vol.14 (12), p.1368-1378

2006

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Energy-efficient soft error-tolerant digital signal processing

IEEE transactions on very large scale integration (VLSI) systems, 2006-04, Vol.14 (4), p.336-348

2006

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Benchmarking In-memory Computing Architectures

IEEE open journal of solid-state circuits, 2022-01, Vol.2, p.1-1

2022

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Necessity of law of balance of moment of moments in non-classical continuum theories for solid continua

Meccanica (Milan), 2018-09, Vol.53 (11-12), p.2939-2972

2018

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High-speed architectures for Reed-Solomon decoders

IEEE transactions on very large scale integration (VLSI) systems, 2001-10, Vol.9 (5), p.641-655

2001

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Reliable low-power digital signal processing via reduced precision redundancy

IEEE transactions on very large scale integration (VLSI) systems, 2004-05, Vol.12 (5), p.497-510

2004

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Deep In-Memory Architectures in SRAM: An Analog Approach to Approximate Computing

Proceedings of the IEEE, 2020-12, Vol.108 (12), p.2251-2275

2020

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A 0.44-μJ/dec, 39.9-μs/dec, Recurrent Attention In-Memory Processor for Keyword Spotting

IEEE journal of solid-state circuits, 2021-07, Vol.56 (7), p.2234-2244

2021

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Binodal, wireless epidermal electronic systems with in-sensor analytics for neonatal intensive care

Science (American Association for the Advancement of Science), 2019-03, Vol.363 (6430)

2019

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Termites: The Neglected Soil Engineers of Tropical Soils

Soil science, 2016-03, Vol.181 (3/4), p.157-165

2016

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A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array

A Variation-Tolerant In-Memory Machine Learning Classifier via On-Chip Training

High-throughput LDPC decoders

A 640-Mb/s 2048-bit programmable LDPC decoder chip

An Energy-Efficient ECG Processor in 45-nm CMOS Using Statistical Error Compensation

Development and initial validation of a theory of planned behavior questionnaire: Assessment of purchase intentions towards products associated with CRM campaigns

Enhancing the Accuracy of 6T SRAM-Based In-Memory Architecture via Maximum Likelihood Detection

Energy-Accuracy Trade-offs for Resistive In-Memory Computing Architectures

Litter Quality Affects Termite Sheeting Production and Water Infiltration in the Soil

Coding for system-on-chip networks: a unified framework

Error-Resilient Low-Power Viterbi Decoder Architectures

Soft N-Modular Redundancy

Signal Processing Methods to Enhance the Energy Efficiency of In-Memory Computing Architectures

Soft digital signal processing

Deep in-Memory Architectures for Machine Learning

Sequential Element Design With Built-In Soft Error Resilience

Energy-efficient soft error-tolerant digital signal processing

Benchmarking In-memory Computing Architectures

Necessity of law of balance of moment of moments in non-classical continuum theories for solid continua

High-speed architectures for Reed-Solomon decoders

Reliable low-power digital signal processing via reduced precision redundancy

Deep In-Memory Architectures in SRAM: An Analog Approach to Approximate Computing

A 0.44-μJ/dec, 39.9-μs/dec, Recurrent Attention In-Memory Processor for Keyword Spotting

Binodal, wireless epidermal electronic systems with in-sensor analytics for neonatal intensive care

Termites: The Neglected Soil Engineers of Tropical Soils

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