UB Paderborn / Katalog / Suche / in CDI

Performance Evaluation of Centralized Reconfigurable Transmitting Power Scheme in Wireless Network-on-chip

Telkomnika, 2018-12, Vol.16 (6), p.2844-2854

2018

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Network Partitioning Domain Knowledge Multiobjective Application Mapping for Large-Scale Network-on-Chip

Applied Computational Intelligence and Soft Computing, 2014-01, Vol.2014 (2014), p.1-10

2014

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Interleaved Incremental/Decremental Support Vector Machine for Embedded System

2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, p.1-5

2019

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Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms

Journal of systems architecture, 2017-02, Vol.73, p.42-52

2017

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Implementation of recurrent neural network algorithm for shortest path calculation in network routing

Proceedings International Symposium on Parallel Architectures, Algorithms and Networks. I-SPAN'02, 2002, p.355-359

2002

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A Particle Swarm Optimization Approach for Routing in VLSI

2010 2nd International Conference on Computational Intelligence, Communication Systems and Networks, 2010, p.49-53

2010

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Network partitioning and GA heuristic crossover for NoC application mapping

2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2013, p.1228-1231

2013

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Hardware transactional memory on multi-processor FPGA platform

2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014, p.2744-2747

2014

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Remote dynamically reconfigurable platform using NetFPGA

2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014, p.1239-1242

2014

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Deadlock detection and avoidance using Signal Interpreted Petri Nets

2012 IEEE International Conference on Circuits and Systems (ICCAS), 2012, p.150-155

2012

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Reconfigurable logic embedded architecture of support vector machine linear kernel

2017 4th International Conference on Electrical Engineering, Computer Science and Informatics (EECSI), 2017, p.1-5

2017

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Hybrid routing tree with buffer insertion under obstacle constraints

2013 IEEE Student Conference on Research and Developement, 2013, p.411-416

2013

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Simultaneous Routing and Buffer Insertion algorithm for interconnect delay optimization in VLSI layout design

2008 International Conference on Microelectronics, 2008, p.175-178

2008

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An optimization algorithm for simultaneous routing and buffer insertion with delay-power constraints in VLSI layout design

Fifteenth International Symposium on Quality Electronic Design, 2014, p.357-364

2014

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Sleep Apnea Event Detection System Based on Heart Rate Variability Analysis

Proceedings of the International Conference on Data Engineering 2015 (DaEng-2015), p.629-637

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Adaptive Configurable Transactional Memory for Multi-processor FPGA Platforms

2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, 2015, p.102-102

2015

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s.RABILA2: An optimal VLSI routing algorithm with buffer insertion using iterative RLC model

2012 IEEE International Conference on Circuits and Systems (ICCAS), 2012, p.48-53

2012

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Optimizing multi-constraint VLSI interconnect routing

Proceedings of the 2009 12th International Symposium on Integrated Circuits, 2009, p.655-658

2009

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A Two-Step Binary Particle Swarm Optimization Approach for Routing in VLSI with Iterative RLC Delay Model

2011 Third International Conference on Computational Intelligence, Modelling & Simulation, 2011, p.63-67

2011

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Pulse coded neural network implementation in VLSI

2000 TENCON Proceedings. Intelligent Systems and Technologies for the New Millennium (Cat. No.00CH37119), 2000, Vol.3, p.237-241 vol.3

2000

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Mixed signal neural circuits for shortest path computation

Conference Record of The Twenty-Ninth Asilomar Conference on Signals, Systems and Computers, 1995, Vol.2, p.876-880 vol.2

1995

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FPGA implementation of RSA public-key cryptographic coprocessor

2000 TENCON Proceedings. Intelligent Systems and Technologies for the New Millennium (Cat. No.00CH37119), 2000, Vol.3, p.6-11 vol.3

2000

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FPGA-Based Real-Time Moving Target Detection System for Unmanned Aerial Vehicle Application

International Journal of Reconfigurable Computing, 2016-01, Vol.2016, p.1-16

2016

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Spatiotemporal neural networks for link-state routing protocols

1996 IEEE International Symposium on Circuits and Systems (ISCAS), 1996, Vol.3, p.547-550 vol.3

1996

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DPLBAnt: Improved load balancing technique based on detection and rerouting of elephant flows in software-defined networks

Computer communications, 2021-12, Vol.180, p.315-327

2021

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Performance Evaluation of Centralized Reconfigurable Transmitting Power Scheme in Wireless Network-on-chip

Network Partitioning Domain Knowledge Multiobjective Application Mapping for Large-Scale Network-on-Chip

Interleaved Incremental/Decremental Support Vector Machine for Embedded System

Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms

Implementation of recurrent neural network algorithm for shortest path calculation in network routing

A Particle Swarm Optimization Approach for Routing in VLSI

Network partitioning and GA heuristic crossover for NoC application mapping

Hardware transactional memory on multi-processor FPGA platform

Remote dynamically reconfigurable platform using NetFPGA

Deadlock detection and avoidance using Signal Interpreted Petri Nets

Reconfigurable logic embedded architecture of support vector machine linear kernel

Hybrid routing tree with buffer insertion under obstacle constraints

Simultaneous Routing and Buffer Insertion algorithm for interconnect delay optimization in VLSI layout design

An optimization algorithm for simultaneous routing and buffer insertion with delay-power constraints in VLSI layout design

Sleep Apnea Event Detection System Based on Heart Rate Variability Analysis

Adaptive Configurable Transactional Memory for Multi-processor FPGA Platforms

s.RABILA2: An optimal VLSI routing algorithm with buffer insertion using iterative RLC model

Optimizing multi-constraint VLSI interconnect routing

A Two-Step Binary Particle Swarm Optimization Approach for Routing in VLSI with Iterative RLC Delay Model

Pulse coded neural network implementation in VLSI

Mixed signal neural circuits for shortest path computation

FPGA implementation of RSA public-key cryptographic coprocessor

FPGA-Based Real-Time Moving Target Detection System for Unmanned Aerial Vehicle Application

Spatiotemporal neural networks for link-state routing protocols

DPLBAnt: Improved load balancing technique based on detection and rerouting of elephant flows in software-defined networks

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