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An Integrated Row-Based Cell Placement and Interconnect Synthesis Tool for Large SFQ Logic Circuits

IEEE transactions on applied superconductivity, 2017-06, Vol.27 (4), p.1-8

2017

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Optimization of quantum circuits for interaction distance in linear nearest neighbor architectures

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 2013, p.1-6

2013

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A placement algorithm for superconducting logic circuits based on cell grouping and super-cell placement

2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, p.1465-1468

2018

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Low write-energy STT-MRAMs using FinFET-based access transistors

2014 IEEE 32nd International Conference on Computer Design (ICCD), 2014, p.374-379

2014

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A Cross-Layer Framework for Designing and Optimizing Deeply-Scaled FinFET-Based Cache Memories

Journal of low power electronics and applications, 2015, Vol.5 (3), p.165-182

2015

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Qubit placement to minimize communication overhead in 2D quantum architectures

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 2014, p.495-500

2014

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Constant-Factor Optimization of Quantum Adders on 2D Quantum Architectures

Reversible Computation, 2013, p.58-69

2013

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A New Approach for Analyzing Functional Neuroimaging Data Using a Combination of CNN-LSTM and Occlusion Sensitivity Analysis to Identify Important Brain Regions in Visual Mental Imagery

Frontiers in biomedical technologies, 2024-07

2024

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SFQmap: A Technology Mapping Tool for Single Flux Quantum Logic Circuits

2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, p.1-5

2018

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AutoRetouch: Automatic Professional Face Retouching

2021 IEEE Winter Conference on Applications of Computer Vision (WACV), 2021, p.989-997

2021

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Energy-efficient cache memories using a dual-Vt 4T SRAM cell with read-assist techniques

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, p.457-462

2016

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Squash 2: a hierarchical scalable quantum mapper considering ancilla sharing

Quantum information & computation, 2016-03, Vol.16 (3&4), p.332-356

2016

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Minimizing the energy-delay product of SRAM arrays using a device-circuit-architecture co-optimization framework

2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2016, p.1-6

2016

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Pilot Register File: Energy Efficient Partitioned Register File for GPUs

2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2017, p.589-600

2017

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Cofactor Sharing for Reversible Logic Synthesis

ACM journal on emerging technologies in computing systems, 2014-11, Vol.11 (2), p.1-21

2014

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Gate-all-around FET based 6T SRAM design using a device-circuit co-optimization framework

2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017, p.1113-1116

2017

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Real-Time Human Motion Capture with Multiple Depth Cameras

2016 13th Conference on Computer and Robot Vision (CRV), 2016, p.24-31

2016

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A thermally-aware energy minimization methodology for global interconnects

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017, p.1213-1218

2017

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Reversible logic synthesis of k-input, m-output lookup tables

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, p.1235-1240

2013

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5nm FinFET Standard Cell Library Optimization and Circuit Synthesis in Near-and Super-Threshold Voltage Regimes

2014 IEEE Computer Society Annual Symposium on VLSI, 2014, p.424-429

2014

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MASAGA: A Linearly-Convergent Stochastic First-Order Method for Optimization on Manifolds

Machine Learning and Knowledge Discovery in Databases, 2019, Vol.11052, p.344-359

2019

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Analyzing the Dark Silicon Phenomenon in a Many-Core Chip Multi-Processor under Deeply-Scaled Process Technologies

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 2015, p.127-132

2015

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A cross-layer design framework and comparative analysis of SRAM cells and cache memories using 7nm FinFET devices

2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014, p.1-2

2014

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Design of multiple fanout clock distribution network for rapid single flux quantum technology

2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 2017, p.384-389

2017

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Design of Complex Rapid Single-Flux-Quantum Cells with Application to Logic Synthesis

2017 16th International Superconductive Electronics Conference (ISEC), 2017, p.1-3

2017

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An Integrated Row-Based Cell Placement and Interconnect Synthesis Tool for Large SFQ Logic Circuits

Optimization of quantum circuits for interaction distance in linear nearest neighbor architectures

A placement algorithm for superconducting logic circuits based on cell grouping and super-cell placement

Low write-energy STT-MRAMs using FinFET-based access transistors

A Cross-Layer Framework for Designing and Optimizing Deeply-Scaled FinFET-Based Cache Memories

Qubit placement to minimize communication overhead in 2D quantum architectures

Constant-Factor Optimization of Quantum Adders on 2D Quantum Architectures

A New Approach for Analyzing Functional Neuroimaging Data Using a Combination of CNN-LSTM and Occlusion Sensitivity Analysis to Identify Important Brain Regions in Visual Mental Imagery

SFQmap: A Technology Mapping Tool for Single Flux Quantum Logic Circuits

AutoRetouch: Automatic Professional Face Retouching

Energy-efficient cache memories using a dual-Vt 4T SRAM cell with read-assist techniques

Squash 2: a hierarchical scalable quantum mapper considering ancilla sharing

Minimizing the energy-delay product of SRAM arrays using a device-circuit-architecture co-optimization framework

Pilot Register File: Energy Efficient Partitioned Register File for GPUs

Cofactor Sharing for Reversible Logic Synthesis

Gate-all-around FET based 6T SRAM design using a device-circuit co-optimization framework

Real-Time Human Motion Capture with Multiple Depth Cameras

A thermally-aware energy minimization methodology for global interconnects

Reversible logic synthesis of k-input, m-output lookup tables

5nm FinFET Standard Cell Library Optimization and Circuit Synthesis in Near-and Super-Threshold Voltage Regimes

MASAGA: A Linearly-Convergent Stochastic First-Order Method for Optimization on Manifolds

Analyzing the Dark Silicon Phenomenon in a Many-Core Chip Multi-Processor under Deeply-Scaled Process Technologies

A cross-layer design framework and comparative analysis of SRAM cells and cache memories using 7nm FinFET devices

Design of multiple fanout clock distribution network for rapid single flux quantum technology

Design of Complex Rapid Single-Flux-Quantum Cells with Application to Logic Synthesis

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