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Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell Elements

IEEE transactions on computer-aided design of integrated circuits and systems, 2009-03, Vol.28 (3), p.327-339

2009

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HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures

IEEE transactions on very large scale integration (VLSI) systems, 2012-04, Vol.20 (4), p.593-604

2012

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Clock Gating Synthesis of Pulsed-Latch Circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 2012-07, Vol.31 (7), p.1019-1030

2012

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Pulse Width Allocation and Clock Skew Scheduling: Optimizing Sequential Circuits Based on Pulsed Latches

IEEE transactions on computer-aided design of integrated circuits and systems, 2010-03, Vol.29 (3), p.355-366

2010

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Retiming Pulsed-Latch Circuits With Regulating Pulse Width

IEEE transactions on computer-aided design of integrated circuits and systems, 2011-08, Vol.30 (8), p.1114-1127

2011

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HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures

IEEE transactions on computer-aided design of integrated circuits and systems, 2010-05, Vol.29 (5), p.657-670

2010

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Register allocation for high-level synthesis using dual supply voltages

2009 46th ACM/IEEE Design Automation Conference, 2009, p.937-942

2009

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Exploring the opportunity of optimizing sequencing elements in ASIC designs

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011, p.1-4

2011

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Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements

2008 45th ACM/IEEE Design Automation Conference, 2008, p.600-605

2008

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HLS-l: high-level synthesis of high performance latch-based circuits

Proceedings of the Conference on Design, Automation and Test in Europe, 2009, p.1112-1117

2009

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HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning

IEEE transactions on circuits and systems. I, Regular papers, 2014-01, Vol.61 (1), p.146-159

2014

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Pulsed-Latch Circuits: A New Dimension in ASIC Design

IEEE design & test of computers, 2011-11, Vol.28 (6), p.50-57

2011

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Wakeup scheduling and its buffered tree synthesis for power gating circuits

Integration (Amsterdam), 2016-03, Vol.53, p.157-170

2016

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Pulser gating: A clock gating of pulsed-latch circuits

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 2011, p.190-195

2011

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Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2011, p.640-646

2011

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Pulsed-latch circuits to push the envelope of ASIC design

2010 International SoC Design Conference, 2010, p.150-153

2010

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Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power

Proceedings of the International Conference on Computer-Aided Design, 2011, p.640-646

2011

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Wakeup synthesis and its buffered tree construction for power gating circuit designs

2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED), 2010, p.413-418

2010

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Retiming and time borrowing: optimizing high-performance pulsed-latch-based circuits

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers, 2009, p.375-380

2009

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Selectively patterned masks: Structured ASIC with asymptotically ASIC performance

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 2011, p.376-381

2011

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Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits

2008 IEEE/ACM International Conference on Computer-Aided Design, 2008, p.224-229

2008

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Statistical time borrowing for pulsed-latch circuit designs

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 2010, p.675-680

2010

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Selectively patterned masks: Beyond structured ASIC

2010 International SoC Design Conference, 2010, p.154-157

2010

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Bounded potential slack: Enabling time budgeting for dual-Vt allocation of hierarchical design

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 2010, p.581-586

2010

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HLS-l: High-level synthesis of high performance latch-based circuits

2009 Design, Automation & Test in Europe Conference & Exhibition, 2009, p.1112-1117

2009

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Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell Elements

HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures

Clock Gating Synthesis of Pulsed-Latch Circuits

Pulse Width Allocation and Clock Skew Scheduling: Optimizing Sequential Circuits Based on Pulsed Latches

Retiming Pulsed-Latch Circuits With Regulating Pulse Width

HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures

Register allocation for high-level synthesis using dual supply voltages

Exploring the opportunity of optimizing sequencing elements in ASIC designs

Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements

HLS-l: high-level synthesis of high performance latch-based circuits

HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning

Pulsed-Latch Circuits: A New Dimension in ASIC Design

Wakeup scheduling and its buffered tree synthesis for power gating circuits

Pulser gating: A clock gating of pulsed-latch circuits

Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power

Pulsed-latch circuits to push the envelope of ASIC design

Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power

Wakeup synthesis and its buffered tree construction for power gating circuit designs

Retiming and time borrowing: optimizing high-performance pulsed-latch-based circuits

Selectively patterned masks: Structured ASIC with asymptotically ASIC performance

Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits

Statistical time borrowing for pulsed-latch circuit designs

Selectively patterned masks: Beyond structured ASIC

Bounded potential slack: Enabling time budgeting for dual-Vt allocation of hierarchical design

HLS-l: High-level synthesis of high performance latch-based circuits

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