UB Paderborn / Katalog / Suche / in CDI

1 – 25 von 131

Sortiert nach

Fully flexible, lightweight, high performance all-solid-state supercapacitor based on 3-Dimensional-graphene/graphite-paper

Journal of power sources, 2017-01, Vol.337, p.159-165

2017

Volltextzugriff (PDF)

A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-Ranging SAR ADC With On-Chip Background Skew Calibration

IEEE journal of solid-state circuits, 2021-09, Vol.56 (9), p.2691-2700

2021

Volltextzugriff (PDF)

A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique

IEEE journal of solid-state circuits, 2022-09, Vol.57 (9), p.2791-2801

2022

Volltextzugriff (PDF)

A 40 mV Transformer-Reuse Self-Startup Boost Converter With MPPT Control for Thermoelectric Energy Harvesting

IEEE journal of solid-state circuits, 2012-12, Vol.47 (12), p.3055-3067

2012

Volltextzugriff (PDF)

A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC

IEEE journal of solid-state circuits, 2024-08, Vol.59 (8), p.2481-2491

2024

Volltextzugriff (PDF)

A Time-Interleaved 12-b 270-MS/s SAR ADC With Virtual-Timing-Reference Timing-Skew Calibration Scheme

IEEE journal of solid-state circuits, 2018-09, Vol.53 (9), p.2584-2594

2018

Volltextzugriff (PDF)

A 28-nm CMOS 12-Bit 250-MS/s Voltage-Current-Time Domain 3-Stage Pipelined ADC

IEEE transactions on circuits and systems. II, Express briefs, 2020-12, Vol.67 (12), p.2843-2847

2020

Volltextzugriff (PDF)

A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC

IEEE journal of solid-state circuits, 2015-02, Vol.50 (2), p.543-555

2015

Volltextzugriff (PDF)

An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS

IEEE journal of solid-state circuits, 2021-04, Vol.56 (4), p.1216-1226

2021

Volltextzugriff (PDF)

A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS

IEEE journal of solid-state circuits, 2019-09, Vol.54 (9), p.2532-2542

2019

Volltextzugriff (PDF)

A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC

IEEE journal of solid-state circuits, 2016-08, Vol.51 (8), p.1826-1839

2016

Volltextzugriff (PDF)

A Single-Supply CDAC-Based Buffer-Embedding SAR ADC With Skip-Reset Scheme Having Inherent Chopping Capability

IEEE journal of solid-state circuits, 2020-10, Vol.55 (10), p.2660-2669

2020

Volltextzugriff (PDF)

A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs

IEEE journal of solid-state circuits, 2016-10, Vol.51 (10), p.2262-2273

2016

Volltextzugriff (PDF)

A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks

IEEE transactions on circuits and systems. II, Express briefs, 2018-12, Vol.65 (12), p.1904-1908

2018

Volltextzugriff (PDF)

A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling

IEEE journal of solid-state circuits, 2018-04, Vol.53 (4), p.1139-1148

2018

Volltextzugriff (PDF)

A Precise Decibel-Linear Programmable Gain Amplifier Using a Constant Current-Density Function

IEEE transactions on microwave theory and techniques, 2012-09, Vol.60 (9), p.2843-2850

2012

Volltextzugriff (PDF)

Introduction to the Special Section on the 2017 Asian Solid-State Circuits Conference (A-SSCC)

IEEE journal of solid-state circuits, 2018-10, Vol.53 (10), p.2739-2740

2018

Volltextzugriff (PDF)

A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS

IEEE journal of solid-state circuits, 2013-06, Vol.48 (6), p.1429-1441

2013

Volltextzugriff (PDF)

A 4th-Order Continuous-Time Delta-Sigma Modulator With Hybrid Noise-Coupling

IEEE transactions on circuits and systems. II, Express briefs, 2022, Vol.69 (9), p.3635-3639

2022

Volltextzugriff (PDF)

A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation

IEEE journal of solid-state circuits, 2015-10, Vol.50 (10), p.2319-2330

2015

Volltextzugriff (PDF)

Introduction to the Special Issue on the 2017 IEEE International Solid-State Circuits Conference

IEEE journal of solid-state circuits, 2017-12, Vol.52 (12), p.3115-3118

2017

Volltextzugriff (PDF)

A 65-nm CMOS 6-Bit 20 GS/s Time-Interleaved DAC With Full-Binary Sub-DACs

IEEE transactions on circuits and systems. II, Express briefs, 2018-09, Vol.65 (9), p.1154-1158

2018

Volltextzugriff (PDF)

Noise analysis of replica driving technique and its verification to 12-bit 200 MS/s pipelined ADC

IET circuits, devices & systems, 2019-11, Vol.13 (8), p.1277-1283

2019

Volltextzugriff (PDF)

A 40-nm CMOS 7-b 32-GS/s SAR ADC With Background Channel Mismatch Calibration

IEEE transactions on circuits and systems. II, Express briefs, 2020-04, Vol.67 (4), p.610-614

2020

Volltextzugriff (PDF)

A Dual-Imaging Speed-Enhanced CMOS Image Sensor for Real-Time Edge Image Extraction

IEEE journal of solid-state circuits, 2017-09, Vol.52 (9), p.2488-2497

2017

Volltextzugriff (PDF)

1 – 25 von 131

Suche als RSS-Feed

Suchergebnisse filtern

Filter anzeigen

Nur zeigen

Geprüft (Peer-Review)
(70)
Mit Volltextzugriff
(121)

Publikationsform

Sprache

Erscheinungsjahr

n.n

Thema

Science & Technology
(72)
Technology
(71)
Engineering
(68)
Engineering, Electrical & Electronic
(67)
Capacitors
(33)
Switches
(33)
Calibration
(30)
Prototypes
(24)
Cmos
(23)
Power Demand
(21)
Interpolation
(18)
Linearity
(18)
Analog To Digital Converters
(17)
Circuits
(17)
Clocks
(17)
Power Consumption
(17)
Analog-Digital Conversion
(14)
Capacitance
(13)
Integrated Circuits
(13)
Timing
(13)

15 weitere anzeigen...

Weniger anzeigen...

Menü

Weitere Dienste

Einstellungen

Fully flexible, lightweight, high performance all-solid-state supercapacitor based on 3-Dimensional-graphene/graphite-paper

A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-Ranging SAR ADC With On-Chip Background Skew Calibration

A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique

A 40 mV Transformer-Reuse Self-Startup Boost Converter With MPPT Control for Thermoelectric Energy Harvesting

A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC

A Time-Interleaved 12-b 270-MS/s SAR ADC With Virtual-Timing-Reference Timing-Skew Calibration Scheme

A 28-nm CMOS 12-Bit 250-MS/s Voltage-Current-Time Domain 3-Stage Pipelined ADC

A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC

An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS

A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS

A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC

A Single-Supply CDAC-Based Buffer-Embedding SAR ADC With Skip-Reset Scheme Having Inherent Chopping Capability

A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs

A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks

A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling

A Precise Decibel-Linear Programmable Gain Amplifier Using a Constant Current-Density Function

Introduction to the Special Section on the 2017 Asian Solid-State Circuits Conference (A-SSCC)

A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS

A 4th-Order Continuous-Time Delta-Sigma Modulator With Hybrid Noise-Coupling

A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation

Introduction to the Special Issue on the 2017 IEEE International Solid-State Circuits Conference

A 65-nm CMOS 6-Bit 20 GS/s Time-Interleaved DAC With Full-Binary Sub-DACs

Noise analysis of replica driving technique and its verification to 12-bit 200 MS/s pipelined ADC

A 40-nm CMOS 7-b 32-GS/s SAR ADC With Background Channel Mismatch Calibration

A Dual-Imaging Speed-Enhanced CMOS Image Sensor for Real-Time Edge Image Extraction

Suchergebnisse filtern