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FlexRAM: Toward an advanced Intelligent Memory system

2012 IEEE 30th International Conference on Computer Design (ICCD), 2012, p.5-14

2012

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A framework for dynamic energy efficiency and temperature management

Proceedings 33rd Annual IEEE/ACM International Symposium on Microarchitecture. MICRO-33 2000, 2000, p.202-213

2000

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A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth

IEEE journal of solid-state circuits, 1996-11, Vol.31 (11), p.1635-1644, Article 1635

1996

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Low-voltage, high-speed circuit designs for gigabit DRAMs

IEEE journal of solid-state circuits, 1997-05, Vol.32 (5), p.642-648

1997

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Requirement-based design methods for adaptive communications links

Annual ACM IEEE Design Automation Conference: Proceedings of the 41st annual conference on Design automation; 07-11 June 2004, 2004, p.93-98

2004

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Low-power adiabatic computing with NMOS energy recovery logic

Electronics letters, 2000-08, Vol.36 (16), p.1349-1350

2000

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Improved domino structures effective for high performance design

Electronics letters, 1999-03, Vol.35 (5), p.367-368, Article 367

1999

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Periodontal healing using a collagen matrix with periodontal ligament progenitor cells in a dehiscence defect model in beagle dogs

Journal of Periodontal & Implant Science, 2019, 49(4), , pp.215-227

2019

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A semi-custom voltage-island technique and its application to high-speed serial links [CMOS active power reduction]

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03, 2003, p.60-65

2003

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Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips

Intelligent Memory Systems, 2001, p.152-159

2001

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Skew-tolerant high-speed (STHS) domino logic

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 2001, Vol.4, p.154-157 vol. 4

2001

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Novel monoclonal antibody against beta 1 integrin enhances cisplatin efficacy in human lung adenocarcinoma cells

Journal of biomedical research, 2016-01, Vol.30 (3), p.217-224

2016

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New high performance sub-1 V circuit technique with reduced standby current and robust data holding

2000 IEEE International Symposium on Circuits and Systems (ISCAS), 2000, Vol.4, p.65-68 vol.4

2000

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Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 2001, Vol.4, p.1-4 vol. 4

2001

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No-race charge-recycling differential logic (NCDL)

Proceedings Ninth Great Lakes Symposium on VLSI, 1999, p.202-205

1999

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A bootstrapped NMOS charge recovery logic

Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222), 1998, p.30-33

1998

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Time- and cell-type specific changes in iron, ferritin, and transferrin in the gerbil hippocampal CA1 region after transient forebrain ischemia

Neural regeneration research, 2016-06, Vol.11 (6), p.924-930

2016

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NMOS energy recovery logic

Proceedings Ninth Great Lakes Symposium on VLSI, 1999, p.310-313

1999

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New current-mode sense amplifiers for high density DRAM and PIM architectures

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 2001, Vol.4, p.938-941 vol. 4

2001

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Low-power adiabatic computing with NMOS energy recovery logic

Electronics letters, 2000-08, Vol.36 (16), p.1-1

2000

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Design of energy efficient SOC with PIM architecture and deep submicron circuit techniques

Yoo, Seung-Moon

2001

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Variable V/sub CC/ design techniques for battery-operated DRAMs

IEEE journal of solid-state circuits, 1993-04, Vol.28 (4), p.499-503

1993

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Variable < e1 > V < /e1 > (CC) design techniques forbattery-operated DRAMs

IEEE journal of solid-state circuits, 1993-04, Vol.28 (4), p.499-503

1993

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Variable V sub(CC) design techniques for battery-operated DRAM's

IEEE journal of solid-state circuits, 1993-01, Vol.28 (4), p.499-503

1993

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L1 data cache decomposition for energy efficiency

International Symposium on Low Power Electronics and Design: Proceedings of the 2001 international symposium on Low power electronics and design, 2001, p.10-15

2001

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FlexRAM: Toward an advanced Intelligent Memory system

A framework for dynamic energy efficiency and temperature management

A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth

Low-voltage, high-speed circuit designs for gigabit DRAMs

Requirement-based design methods for adaptive communications links

Low-power adiabatic computing with NMOS energy recovery logic

Improved domino structures effective for high performance design

Periodontal healing using a collagen matrix with periodontal ligament progenitor cells in a dehiscence defect model in beagle dogs

A semi-custom voltage-island technique and its application to high-speed serial links [CMOS active power reduction]

Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips

Skew-tolerant high-speed (STHS) domino logic

Novel monoclonal antibody against beta 1 integrin enhances cisplatin efficacy in human lung adenocarcinoma cells

New high performance sub-1 V circuit technique with reduced standby current and robust data holding

Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT

No-race charge-recycling differential logic (NCDL)

A bootstrapped NMOS charge recovery logic

Time- and cell-type specific changes in iron, ferritin, and transferrin in the gerbil hippocampal CA1 region after transient forebrain ischemia

NMOS energy recovery logic

New current-mode sense amplifiers for high density DRAM and PIM architectures

Low-power adiabatic computing with NMOS energy recovery logic

Design of energy efficient SOC with PIM architecture and deep submicron circuit techniques

Variable V/sub CC/ design techniques for battery-operated DRAMs

Variable < e1 > V < /e1 > (CC) design techniques forbattery-operated DRAMs

Variable V sub(CC) design techniques for battery-operated DRAM's

L1 data cache decomposition for energy efficiency

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