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Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product

2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA), 2021, p.43-56

2021

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IEEE_Xplore

Hardware architecture and software stack for PIM based on commercial DRAM technology

Proceedings of the 48th Annual International Symposium on Computer Architecture, 2021, p.43-56

2021

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25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications

2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, Vol.64, p.350-352

2021

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IEEE_Xplore

Architecting to achieve a billion requests per second throughput on a single key-value store server platform

2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA), 2015, p.476-488

2015

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Achieving One Billion Key-Value Requests per Second on a Single Server

IEEE MICRO, 2016-05, Vol.36 (3), p.94-104

2016

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IEEE_Xplore

Full-Stack Architecting to Achieve a Billion-Requests-Per-Second Throughput on a Single Key-Value Store Server Platform

ACM transactions on computer systems, 2016-05, Vol.34 (2), p.1-30

2016

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CiDRA: A cache-inspired DRAM resilience architecture

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA), 2015, p.502-513

2015

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IEEE_Xplore

3D-Xpath: high-density managed DRAM architecture with cost-effective alternative paths for memory transactions

Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, 2018, p.1-12

2018

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Row-buffer decoupling: a case for low-latency DRAM microarchitecture

Proceeding of the 41st annual international symposium on Computer architecuture, 2014, p.337-348

2014

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A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process

2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, Vol.65, p.448-450

2022

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IEEE_Xplore

CIDR: A Cache Inspired Area-Efficient DRAM Resilience Architecture against Permanent Faults

IEEE computer architecture letters, 2015-01, Vol.14 (1), p.17-20

2015

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Exploring energy-efficient DRAM array organizations

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011, p.1-4

2011

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IEEE_Xplore

Row-buffer decoupling: A case for low-latency DRAM microarchitecture

2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA), 2014, p.337-348

2014

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IEEE_Xplore

Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices

2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2017, p.61-72

2017

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IEEE_Xplore

Microbank: architecting through-silicon interposer-based main memory systems

Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, 2014, p.1059-1070

2014

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IEEE_Xplore

History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures

Proceedings of the 29th ACM on International Conference on Supercomputing, 2015, p.251-261

2015

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McSimA+: A manycore simulator with application-level+ simulation and detailed microarchitecture modeling

2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2013, p.74-85

2013

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IEEE_Xplore

Multimodel ensemble forecasting of rainfall over East Asia: regularized regression approach

International journal of climatology, 2014-11, Vol.34 (14), p.3720-3731

2014

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Row-buffer decoupling: a case for low-latency DRAM microarchitecture

Computer architecture news, 2014-10, Vol.42 (3), p.337-348

2014

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Architecting to achieve a billion requests per second throughput on a single key-value store server platform

Computer architecture news, 2016-01, Vol.43 (3S), p.476-488

2016

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Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product

Hardware architecture and software stack for PIM based on commercial DRAM technology

25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications

Architecting to achieve a billion requests per second throughput on a single key-value store server platform

Achieving One Billion Key-Value Requests per Second on a Single Server

Full-Stack Architecting to Achieve a Billion-Requests-Per-Second Throughput on a Single Key-Value Store Server Platform

CiDRA: A cache-inspired DRAM resilience architecture

3D-Xpath: high-density managed DRAM architecture with cost-effective alternative paths for memory transactions

Row-buffer decoupling: a case for low-latency DRAM microarchitecture

A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process

CIDR: A Cache Inspired Area-Efficient DRAM Resilience Architecture against Permanent Faults

Exploring energy-efficient DRAM array organizations

Row-buffer decoupling: A case for low-latency DRAM microarchitecture

Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices

Microbank: architecting through-silicon interposer-based main memory systems

History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures

McSimA+: A manycore simulator with application-level+ simulation and detailed microarchitecture modeling

Multimodel ensemble forecasting of rainfall over East Asia: regularized regression approach

Row-buffer decoupling: a case for low-latency DRAM microarchitecture

Architecting to achieve a billion requests per second throughput on a single key-value store server platform

Energy Awareness in Contemporary Memory Systems

High efficiency n-ZnO/p-Si core–shell nanowire photodiode based on well-ordered Si nanowire array with smooth surface

PS 02-63 CORRELATION OF AMBULATORY BLOOD PRESSURE PARAMETERS AND THE LEFT VENTRICULAR END-DIASTOLIC PRESSURE DURING LEG-RAISE EXERCISE

Organic inverter using two transistors with different channel thicknesses

Semi-transparent organic/inorganic hybrid photo-detector using pentacene/ZnO diode connected to pentacene transistor

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