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A Single-Nucleotide Polymorphism in an Endo-1,4-β-Glucanase Gene Controls Seed Coat Permeability in Soybean

PloS one, 2015-06, Vol.10 (6), p.e0128527

2015

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A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution

IEEE journal of solid-state circuits, 2017-01, Vol.52 (1), p.250-260

2017

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A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface

IEEE journal of solid-state circuits, 2018-01, Vol.53 (1), p.144-154

2018

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Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM

IEEE journal of solid-state circuits, 2018-10, Vol.53 (10), p.2906-2916

2018

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A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking

IEEE journal of solid-state circuits, 2019-01, Vol.54 (1), p.197-209

2019

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A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s

IEEE transactions on circuits and systems. I, Regular papers, 2016-01, Vol.63 (1), p.122-133

2016

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A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme

IEEE journal of solid-state circuits, 2013-01, Vol.48 (1), p.168-177

2013

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A Study on Development of Engine Fault Diagnostic System

Mathematical problems in engineering, 2015-01, Vol.2015 (2015), p.1-6

2015

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A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.206-208

2018

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A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.204-206

2018

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Development of Mode-Switchable Touch Sensor Using MWCNT Composite Conductive Nonwoven Fabric

Polymers, 2022-04, Vol.14 (8), p.1545

2022

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An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

IEEE journal of solid-state circuits, 2008-01, Vol.43 (1), p.121-131, Article 121

2008

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Smart Floor Mats for a Health Monitoring System Based on Textile Pressure Sensing: Development and Usability Study

JMIR formative research, 2023-08, Vol.7, p.e47325-e47325

2023

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Development of the knocking decision system using the CKP signal collection and analysis

International journal of security and networks, 2014, Vol.9 (4), p.209

2014

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Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM

2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2015, p.1-6

2015

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Development of the knocking and the defective cylinder decision system of industrial CRDI diesel engine through the CKP sensor signal analysis

International journal of vehicle design, 2016, Vol.72 (3), p.193

2016

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23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, p.378-380

2019

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An Area-Efficient, Low-VDD, Highly Reliable Multi-Cell Antifuse System Fully Operative in DRAMs

IEICE transactions on electronics, 2011, Vol.E94-C (10), p.1690-1697

2011

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Comparison of the thickness of Longus colli and Sternocleidomastoid according to weight of backpack and measurement of craniocervical angle

Research journal of pharmacy and technology, 2018-07, Vol.11 (7), p.2997-3002

2018

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Development of Algorithms for Efficient Energy Management in the Industrial Common Rail Engine

International journal of control and automation, 2013-10, Vol.6 (5), p.345-352

2013

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A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control

IEEE journal of solid-state circuits, 2005-01, Vol.40 (1), p.223-232

2005

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5.7 A 29nW bandgap reference circuit

2015 IEEE International Solid State Circuits Conference (ISSCC), 2015, p.1-3

2015

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Classification of snoring sound based on a recurrent neural network

Expert systems with applications, 2019-06, Vol.123, p.237-245

2019

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A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme

2012 IEEE International Solid-State Circuits Conference, 2012, p.38-40

2012

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A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008, p.278-613

2008

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A Single-Nucleotide Polymorphism in an Endo-1,4-β-Glucanase Gene Controls Seed Coat Permeability in Soybean

A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution

A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface

Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM

A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking

A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s

A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme

A Study on Development of Engine Fault Diagnostic System

A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

Development of Mode-Switchable Touch Sensor Using MWCNT Composite Conductive Nonwoven Fabric

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

Smart Floor Mats for a Health Monitoring System Based on Textile Pressure Sensing: Development and Usability Study

Development of the knocking decision system using the CKP signal collection and analysis

Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM

Development of the knocking and the defective cylinder decision system of industrial CRDI diesel engine through the CKP sensor signal analysis

23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

An Area-Efficient, Low-VDD, Highly Reliable Multi-Cell Antifuse System Fully Operative in DRAMs

Comparison of the thickness of Longus colli and Sternocleidomastoid according to weight of backpack and measurement of craniocervical angle

Development of Algorithms for Efficient Energy Management in the Industrial Common Rail Engine

A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control

5.7 A 29nW bandgap reference circuit

Classification of snoring sound based on a recurrent neural network

A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme

A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques

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