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Deep Learning Accelerators' Configuration Space Exploration Effect on Performance and Resource Utilization: A Gemmini Case Study

Sensors (Basel, Switzerland), 2023-02, Vol.23 (5), p.2380

2023

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Lightweight and Energy-Efficient Deep Learning Accelerator for Real-Time Object Detection on Edge Devices

Sensors (Basel, Switzerland), 2023-01, Vol.23 (3), p.1185

2023

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FreFlex: A High-Performance Processor for Convolution and Attention Computations via Sparsity-Adaptive Dynamic Frequency Boosting

IEEE journal of solid-state circuits, 2024-03, Vol.59 (3), p.855-866

2024

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52.5 TOPS/W 1.7GHz Reconfigurable XGBoost Inference Accelerator Based on Modular-Unit-Tree with Dynamic Data and Compute Gating

2024 IEEE Custom Integrated Circuits Conference (CICC), 2024, p.1-2

2024

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Memory-efficient SURF architecture for ASIC implementation

Electronics letters, 2014-07, Vol.50 (15), p.1058-1059

2014

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Design of a mixed prime factor FFT for portable digital radio mondiale receiver

IEEE transactions on consumer electronics, 2008-11, Vol.54 (4), p.1590-1594

2008

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An IEEE 802.11g WLAN Digital Baseband Processor Using Hybrid Channel Estimation for Wireless Home A/V Receivers

IEEE transactions on consumer electronics, 2009-08, Vol.55 (3), p.1263-1270

2009

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A real-time stereo depth extraction hardware for intelligent home assistant robot

IEEE transactions on consumer electronics, 2010-08, Vol.56 (3), p.1782-1788

2010

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Electrical characteristics of poly(3-hexylthiophene) organic thin film transistor with electroplated metal gate electrodes on polyimide

Thin solid films, 2007-04, Vol.515 (12), p.5065-5069

2007

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A Flexible Machine Vision AI System for Edge-Oriented Deep Learning Accelerators

2023 International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC), 2023, p.1-4

2023

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An Efficient NPU-Aware Filter Pruning in Convolutional Neural Network

2023 International Conference on Electronics, Information, and Communication (ICEIC), 2023, p.1-3

2023

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Implementation of a H.264/AVC SVC decoder with multi-symbol prediction CAVLC for advanced T-DMB receiver

IEEE transactions on consumer electronics, 2010-11, Vol.56 (4), p.2819-2825

2010

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Optimization Method and Implementation of Fake Quantization from the Perspective of Hardware Performance

2023 International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC), 2023, p.1-2

2023

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Extended least square unbiased FIR filter for target tracking using the constant velocity motion model

International journal of control, automation, and systems, 2017-04, Vol.15 (2), p.947-951

2017

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A Selective Multi-Unit Group Filter-Based Flexible Fast Light-CNN Training

2023 International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC), 2023, p.1-4

2023

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Deep Neural Network Dataset Collection for Optimal Positioning of a Capacitive Compensated Schiffman Phase Shifter

2023 International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC), 2023, p.1-6

2023

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A Novel Low-Cost High-Throughput CAVLC Decoder for H.264/AVC

IEICE Transactions on Information and Systems, 2011/04/01, Vol.E94.D(4), pp.895-904

2011

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An efficient recursive cell architecture of modified Euclid's algorithm for decoding Reed-Solomon codes

IEEE transactions on consumer electronics, 2002-11, Vol.48 (4), p.845-849

2002

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Memory optimization of bilateral filter and its hardware implementation

The 18th IEEE International Symposium on Consumer Electronics (ISCE 2014), 2014, p.1-2

2014

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Object Detection Network Robust to Local Illumination Variations

2021 18th International SoC Design Conference (ISOCC), 2021, p.87-88

2021

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Implementation of a Round Robin Processing Element for Deep Learning Accelerator

2020 International SoC Design Conference (ISOCC), 2020, p.302-303

2020

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Memory-Centric Architecture of Neural Processing Unit for Edge Device

2021 18th International SoC Design Conference (ISOCC), 2021, p.240-241

2021

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Improved mutation method for providing high genetic diversity of genetic algorithm processor

IEICE Electronics Express, 2012-01, Vol.9 (9), p.822-827

2012

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Exploring GEMM Operations on Different Configurations of the Gemmini Accelerator

2022 19th International SoC Design Conference (ISOCC), 2022, p.356-357

2022

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NPU-aware Parameter Generation in Quantization ONNX Model

2021 IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia), 2021, p.1-3

2021

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Deep Learning Accelerators' Configuration Space Exploration Effect on Performance and Resource Utilization: A Gemmini Case Study

Lightweight and Energy-Efficient Deep Learning Accelerator for Real-Time Object Detection on Edge Devices

FreFlex: A High-Performance Processor for Convolution and Attention Computations via Sparsity-Adaptive Dynamic Frequency Boosting

52.5 TOPS/W 1.7GHz Reconfigurable XGBoost Inference Accelerator Based on Modular-Unit-Tree with Dynamic Data and Compute Gating

Memory-efficient SURF architecture for ASIC implementation

Design of a mixed prime factor FFT for portable digital radio mondiale receiver

An IEEE 802.11g WLAN Digital Baseband Processor Using Hybrid Channel Estimation for Wireless Home A/V Receivers

A real-time stereo depth extraction hardware for intelligent home assistant robot

Electrical characteristics of poly(3-hexylthiophene) organic thin film transistor with electroplated metal gate electrodes on polyimide

A Flexible Machine Vision AI System for Edge-Oriented Deep Learning Accelerators

An Efficient NPU-Aware Filter Pruning in Convolutional Neural Network

Implementation of a H.264/AVC SVC decoder with multi-symbol prediction CAVLC for advanced T-DMB receiver

Optimization Method and Implementation of Fake Quantization from the Perspective of Hardware Performance

Extended least square unbiased FIR filter for target tracking using the constant velocity motion model

A Selective Multi-Unit Group Filter-Based Flexible Fast Light-CNN Training

Deep Neural Network Dataset Collection for Optimal Positioning of a Capacitive Compensated Schiffman Phase Shifter

A Novel Low-Cost High-Throughput CAVLC Decoder for H.264/AVC

An efficient recursive cell architecture of modified Euclid's algorithm for decoding Reed-Solomon codes

Memory optimization of bilateral filter and its hardware implementation

Object Detection Network Robust to Local Illumination Variations

Implementation of a Round Robin Processing Element for Deep Learning Accelerator

Memory-Centric Architecture of Neural Processing Unit for Edge Device

Improved mutation method for providing high genetic diversity of genetic algorithm processor

Exploring GEMM Operations on Different Configurations of the Gemmini Accelerator

NPU-aware Parameter Generation in Quantization ONNX Model

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