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Interpage-Based Endurance-Enhancing Lower State Encoding for MLC and TLC Flash Memory Storages
IEEE transactions on very large scale integration (VLSI) systems, 2019-09, Vol.27 (9), p.2033-2045
2019
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Designing a Resilient L1 Cache Architecture to Process Variation-Induced Access-Time Failures
IEEE transactions on computers, 2016-10, Vol.65 (10), p.2999-3012
2016
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A Case Study of Quantizing Convolutional Neural Networks for Fast Disease Diagnosis on Portable Medical Devices
Sensors (Basel, Switzerland), 2021-12, Vol.22 (1), p.219
2021
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A Low-Cost Mechanism Exploiting Narrow-Width Values for Tolerating Hard Faults in ALU
IEEE transactions on computers, 2015-09, Vol.64 (9), p.2433-2446
2015
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Pinning Page Structure Entries to Last-Level Cache for Fast Address Translation
IEEE access, 2022, Vol.10, p.1-1
2022
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Ensuring Cache Reliability and Energy Scaling at Near-Threshold Voltage With Macho
IEEE transactions on computers, 2015-06, Vol.64 (6), p.1694-1706
2015
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Proactively Invalidating Dead Blocks to Enable Fast Writes in STT-MRAM Caches
IEEE access, 2022, Vol.10, p.29419-29431
2022
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On the Positional Single Error Correction and Double Error Detection in Racetrack Memories
IEEE access, 2023, Vol.11, p.18300-18310
2023
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SAVector: Vectored Systolic Arrays
IEEE access, 2024-01, Vol.12, p.1-1
2024
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Partial Row Activation for Low-Power DRAM System
2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2017, p.217-228
2017
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Attaché: towards ideal memory compression by mitigating metadata bandwidth overheads
2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2018, p.326-338
2018
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Ternary cache: Three-valued MLC STT-RAM caches
2014 IEEE 32nd International Conference on Computer Design (ICCD), 2014, p.83-89
2014
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On-the-Fly Lowering Engine: Offloading Data Layout Conversion for Convolutional Neural Networks
IEEE access, 2022, Vol.10, p.79730-79746
2022
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Residue cache: a low-energy low-area L2 cache architecture via compression and partial hits
2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2011, p.420-429
2011
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Skinflint DRAM system: Minimizing DRAM chip writes for low power
2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), 2013, p.25-34
2013
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CID: Co-Architecting Instruction Cache and Decompression System for Embedded Systems
IEEE transactions on computers, 2021-07, Vol.70 (7), p.1132-1145
2021
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Macho: A failure model-oriented adaptive cache architecture to enable near-threshold voltage scaling
2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), 2013, p.532-541
2013
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Lizard: Energy-efficient hard fault detection, diagnosis and isolation in the ALU
2010 IEEE International Conference on Computer Design, 2010, p.342-349
2010
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Enhanced Positional SECDED: Achieving Maximal Double-Error Correction in Racetrack Memories
IEEE transactions on magnetics, 2024-03, Vol.60 (3), p.1-10
2024
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Conveyor: Towards Asynchronous Dataflow in Systolic Array to Exploit Unstructured Sparsity
2023 IEEE 41st International Conference on Computer Design (ICCD), 2023, p.423-431
2023
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ADAM: Adaptive Block Placement with Metadata Embedding for Hybrid Caches
2020 IEEE 38th International Conference on Computer Design (ICCD), 2020, p.421-424
2020
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TLB index-based tagging for cache energy reduction
IEEE/ACM International Symposium on Low Power Electronics and Design, 2011, p.85-90
2011
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Exploiting Data Compression for Adaptive Block Placement in Hybrid Caches
Electronics (Basel), 2022-01, Vol.11 (2), p.240
2022
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SparseFT: Sparsity-aware Fault Tolerance for Reliable CNN Inference on GPUs
2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT), 2023, p.337-338
2023
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Touché: Towards Ideal and Efficient Cache Compression By Mitigating Tag Area Overheads
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019, p.453-465
2019
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