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An Analog-Assisted Tri-Loop Digital Low-Dropout Regulator

IEEE journal of solid-state circuits, 2018-01, Vol.53 (1), p.20-34

2018

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A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS

IEEE journal of solid-state circuits, 2010-06, Vol.45 (6), p.1111-1121

2010

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A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH \Delta \Sigma Modulator With Multirate Opamp Sharing

IEEE transactions on circuits and systems. I, Regular papers, 2017-10, Vol.64 (10), p.2641-2654

2017

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A Fully Integrated Digital LDO With Coarse-Fine-Tuning and Burst-Mode Operation

IEEE transactions on circuits and systems. II, Express briefs, 2016-07, Vol.63 (7), p.683-687

2016

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A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration

IEEE journal of solid-state circuits, 2018-03, Vol.53 (3), p.850-860

2018

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A Wide Input Range Dual-Path CMOS Rectifier for RF Energy Harvesting

IEEE transactions on circuits and systems. II, Express briefs, 2017-02, Vol.64 (2), p.166-170

2017

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A 2.63 μW ECG Processor With Adaptive Arrhythmia Detection and Data Compression for Implantable Cardiac Monitoring Device

IEEE transactions on biomedical circuits and systems, 2021-08, Vol.15 (4), p.777-790

2021

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An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS

IEEE journal of solid-state circuits, 2016-05, Vol.51 (5), p.1223-1234

2016

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A Dual-Output Wireless Power Transfer System With Active Rectifier and Three-Level Operation

IEEE transactions on power electronics, 2017-02, Vol.32 (2), p.927-930

2017

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A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC

IEEE journal of solid-state circuits, 2016-02, Vol.51 (2), p.365-377

2016

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60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration

IEEE journal of solid-state circuits, 2017-10, Vol.52 (10), p.2576-2588

2017

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A 312 ps response-time LDO with enhanced super source follower in 28 nm CMOS

Electronics letters, 2016-08, Vol.52 (16), p.1368-1370

2016

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A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations

IEEE transactions on very large scale integration (VLSI) systems, 2017-01, Vol.25 (1), p.354-363

2017

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Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators

IEEE transactions on circuits and systems. II, Express briefs, 2016-09, Vol.63 (9), p.903-907

2016

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Active–Passive \Delta \Sigma Modulator for High-Resolution and Low-Power Applications

IEEE transactions on very large scale integration (VLSI) systems, 2017-01, Vol.25 (1), p.364-374

2017

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Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs

IEEE transactions on circuits and systems. I, Regular papers, 2015-09, Vol.62 (9), p.2196-2206

2015

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Accuracy-Enhanced Variance-Based Time-Skew Calibration Using SAR as Window Detector

IEEE transactions on very large scale integration (VLSI) systems, 2019-02, Vol.27 (2), p.481-485

2019

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Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology

IEEE transactions on circuits and systems. I, Regular papers, 2018-06, Vol.65 (6), p.1819-1829

2018

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An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC

IEEE journal of solid-state circuits, 2012-11, Vol.47 (11), p.2763-2772

2012

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Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC With Optimal Code Transfer Technique

IEEE transactions on circuits and systems. I, Regular papers, 2019-02, Vol.66 (2), p.489-501

2019

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Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC

IEEE transactions on very large scale integration (VLSI) systems, 2016-03, Vol.24 (3), p.1203-1207

2016

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A 550- \mu W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental \Sigma\Delta ADC With 256 Clock Cycles in 65-nm CMOS

IEEE journal of solid-state circuits, 2019-04, Vol.54 (4), p.1161-1172

2019

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DCM operation analysis of 3-level boost converters

Electronics letters, 2017-02, Vol.53 (4), p.270-272

2017

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Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC

IEEE transactions on very large scale integration (VLSI) systems, 2016-07, Vol.24 (7), p.2603-2607

2016

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Reconfigurable mismatch-free time-interleaved bandpass sigma–delta modulator for wireless communications

Electronics letters, 2017-03, Vol.53 (7), p.506-508

2017

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An Analog-Assisted Tri-Loop Digital Low-Dropout Regulator

A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS

A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH \Delta \Sigma Modulator With Multirate Opamp Sharing

A Fully Integrated Digital LDO With Coarse-Fine-Tuning and Burst-Mode Operation

A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration

A Wide Input Range Dual-Path CMOS Rectifier for RF Energy Harvesting

A 2.63 μW ECG Processor With Adaptive Arrhythmia Detection and Data Compression for Implantable Cardiac Monitoring Device

An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS

A Dual-Output Wireless Power Transfer System With Active Rectifier and Three-Level Operation

A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC

60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration

A 312 ps response-time LDO with enhanced super source follower in 28 nm CMOS

A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations

Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators

Active–Passive \Delta \Sigma Modulator for High-Resolution and Low-Power Applications

Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs

Accuracy-Enhanced Variance-Based Time-Skew Calibration Using SAR as Window Detector

Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology

An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC

Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC With Optimal Code Transfer Technique

Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC

A 550- \mu W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental \Sigma\Delta ADC With 256 Clock Cycles in 65-nm CMOS

DCM operation analysis of 3-level boost converters

Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC

Reconfigurable mismatch-free time-interleaved bandpass sigma–delta modulator for wireless communications

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