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Formal verification by symbolic evaluation of partially-ordered trajectories

Formal methods in system design, 1995-03, Vol.6 (2), p.147-189

1995

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Introduction to generalized symbolic trajectory evaluation

IEEE transactions on very large scale integration (VLSI) systems, 2003-06, Vol.11 (3), p.345-353

2003

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On the existence of speed-independent circuits

Theoretical computer science, 1991-09, Vol.86 (2), p.343-364

Seger, C.-J.

1991

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Connecting Bits with Floating-Point Numbers: Model Checking and Theorem Proving in Practice

Automated Deduction - CADE-17, 2000, p.235-235

2000

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A unified framework for race analysis of asynchronous networks

Journal of the ACM, 1989, Vol.36 (1), p.20-45

1989

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An industrially effective environment for formal hardware verification

IEEE transactions on computer-aided design of integrated circuits and systems, 2005-09, Vol.24 (9), p.1381-1405

2005

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The completeness of a hardware inference system

Computer Aided Verification, 2005, p.286-298

2005

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Generalized ternary simulation of sequential circuits

RAIRO. Informatique théorique et applications, 1994, Vol.28 (3-4), p.159-186

1994

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An optimistic ternary simulation of gate races

Theoretical computer science, 1988-01, Vol.61 (1), p.49-66

1988

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Correspondence between ternary simulation and binary race analysis in gate networks

Automata, Languages and Programming, 1986, p.69-78

1986

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Serious Toxicity in an Infant Due to Ingestion of 1 mg Risperidone

Clinical Toxicology, 2008, Vol.46 (7), p.629-629

2008

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Automatic verification of asynchronous circuits

IEEE design & test of computers, 1995, Vol.12 (1), p.24-31, Article 24

1995

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A Characterization of Ternary Simulation of Gate Networks

IEEE transactions on computers, 1987-11, Vol.C-36 (11), p.1318-1327

1987

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Robust Storage Structures for Crash Recovery

IEEE transactions on computers, 1986-04, Vol.C-35 (4), p.288-295

1986

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Practical formal verification in microprocessor design

IEEE design & test of computers, 2001-07, Vol.18 (4), p.16-25

2001

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A simple theorem prover based on symbolic trajectory evaluation and BDD's

IEEE transactions on computer-aided design of integrated circuits and systems, 1995-04, Vol.14 (4), p.413-422

1995

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Automatic verification of refinement

Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1994, p.226-229

1994

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Lifted-FL: A Pragmatic Implementation of Combined Model Checking and Theorem Proving

Lecture notes in computer science, 1999, Vol.1690, p.323-340

1999

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Model checking lattices: using and reasoning about information orders for abstraction

Logic journal of the IGPL, 1999-05, Vol.7 (3), p.375-411

1999

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Ternary simulation of asynchronous gate networks

Seger, C.-J

1986

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A bounded delay race model

1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers, 1989, p.130-133

Seger, C.-J.

1989

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Dialogic Feedback for High Impact Learning: Key to PCP-Coaching and Assessment-as-Learning

1st, 2023

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Risk Factors for Adverse Drug Events Among Older Adults in the Ambulatory Setting

Journal of the American Geriatrics Society (JAGS), 2004-08, Vol.52 (8), p.1349-1354

2004

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Creating Impact through Future Learning: The High Impact Learning that Lasts (HILL) Model

1, 2018

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Identification of single gene deletions at 15q13.3: further evidence that CHRNA7 causes the 15q13.3 microdeletion syndrome phenotype

Clinical genetics, 2013-04, Vol.83 (4), p.345-351

2013

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Formal verification by symbolic evaluation of partially-ordered trajectories

Introduction to generalized symbolic trajectory evaluation

On the existence of speed-independent circuits

Connecting Bits with Floating-Point Numbers: Model Checking and Theorem Proving in Practice

A unified framework for race analysis of asynchronous networks

An industrially effective environment for formal hardware verification

The completeness of a hardware inference system

Generalized ternary simulation of sequential circuits

An optimistic ternary simulation of gate races

Correspondence between ternary simulation and binary race analysis in gate networks

Serious Toxicity in an Infant Due to Ingestion of 1 mg Risperidone

Automatic verification of asynchronous circuits

A Characterization of Ternary Simulation of Gate Networks

Robust Storage Structures for Crash Recovery

Practical formal verification in microprocessor design

A simple theorem prover based on symbolic trajectory evaluation and BDD's

Automatic verification of refinement

Lifted-FL: A Pragmatic Implementation of Combined Model Checking and Theorem Proving

Model checking lattices: using and reasoning about information orders for abstraction

Ternary simulation of asynchronous gate networks

A bounded delay race model

Dialogic Feedback for High Impact Learning: Key to PCP-Coaching and Assessment-as-Learning

Risk Factors for Adverse Drug Events Among Older Adults in the Ambulatory Setting

Creating Impact through Future Learning: The High Impact Learning that Lasts (HILL) Model

Identification of single gene deletions at 15q13.3: further evidence that CHRNA7 causes the 15q13.3 microdeletion syndrome phenotype

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