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Rigorous Surface-Potential Solution for Undoped Symmetric Double-Gate MOSFETs Considering Both Electrons and Holes at Quasi NonEquilibrium

IEEE transactions on electron devices, 2008-02, Vol.55 (2), p.616-623

2008

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A Compact Model for Undoped Silicon-Nanowire MOSFETs With Schottky-Barrier Source/Drain

IEEE transactions on electron devices, 2009-05, Vol.56 (5), p.1100-1109

2009

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"Ground-Referenced" Model for Three-Terminal Symmetric Double-Gate MOSFETs With Source/Drain Symmetry

IEEE transactions on electron devices, 2008-09, Vol.55 (9), p.2526-2530

2008

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A Compact Model Satisfying Gummel Symmetry in Higher Order Derivatives and Applicable to Asymmetric MOSFETs

IEEE transactions on electron devices, 2008-02, Vol.55 (2), p.624-631

2008

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A New Impact-Ionization Current Model Applicable to Both Bulk and SOI MOSFETs by Considering Self-Lattice-Heating

IEEE transactions on electron devices, 2008-09, Vol.55 (9), p.2378-2385

2008

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Under-Bump Metallization Contact Resistance ( R ) Characterization at 10- \mu \text Polymer Passivation Opening

IEEE transactions on components, packaging, and manufacturing technology (2011), 2017-10, Vol.7 (10), p.1592-1597

2017

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Physics-based single-piece charge model for strained-Si MOSFETs

IEEE transactions on electron devices, 2005-07, Vol.52 (7), p.1555-1562

2005

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Surface-Potential Solution for Generic Undoped MOSFETs With Two Gates

IEEE transactions on electron devices, 2007-01, Vol.54 (1), p.169-172

2007

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Implicit Analytical Surface/Interface Potential Solutions for Modeling Strained-Si MOSFETs

IEEE transactions on electron devices, 2006-12, Vol.53 (12), p.3110-3117

2006

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Effect of substrate doping on the capacitance-Voltage characteristics of strained-silicon pMOSFETs

IEEE electron device letters, 2006-01, Vol.27 (1), p.62-64

2006

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Subcircuit Compact Model for Dopant-Segregated Schottky Gate-All-Around Si-Nanowire MOSFETs

IEEE transactions on electron devices, 2010-04, Vol.57 (4), p.772-781

2010

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Explicit Compact Surface-Potential and Drain-Current Models for Generic Asymmetric Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistors

Japanese Journal of Applied Physics, 2007-04, Vol.46 (4S), p.2067

2007

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Fine-Pitch RDL Integration for Fan-Out Wafer-Level Packaging

2020 IEEE 70th Electronic Components and Technology Conference (ECTC), 2020, p.1126-1131

2020

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Evaluation on multiple layer PBO-based Cu RDL process for Fan-Out Wafer Level Packaging (FOWLP)

2016 IEEE 18th Electronics Packaging Technology Conference (EPTC), 2016, p.662-665

2016

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aGround-Referenceda Model for Three-Terminal Symmetric Double-Gate MOSFETs With Source/Drain Symmetry

IEEE transactions on electron devices, 2008-01, Vol.55 (9)

2008

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Extraction of physical parameters of strained silicon MOSFETs from C-V measurement

Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005, 2005, p.521-524

2005

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Unification of MOS compact models with the unified regional modeling approach

Journal of computational electronics, 2011-06, Vol.10 (1-2), p.121-135

2011

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Unification of MOS compact models with the unified regional modeling approach : Computational Electronics in Asia and Selected Papers from IWCE 2009 in Beijing

Journal of computational electronics, 2011, Vol.10 (1-2), p.121-135

2011

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Unified regional modeling approach to emerging multiple-gate/nanowire MOSFETs

2008 9th International Conference on Solid-State and Integrated-Circuit Technology, 2008, p.262-267

2008

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Unified compact modeling for Bulk/SOI/FinFET/SiNW MOSFETs

2009 2nd International Workshop on Electron Devices and Semiconductor Technology, 2009, p.1-6

2009

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RF spiral planar inductor designs - preliminary results [RFIC applications]

Asia-Pacific Conference on Applied Electromagnetics, 2003. APACE 2003, 2003, p.16-20

2003

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A new impact ionization current model applicable to both bulk and SOI MOSFETs by considering self-lattice-heating

2007 International Semiconductor Device Research Symposium, 2007, p.1-2

2007

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Unified Compact Modeling of Emerging Multiple-Gate MOSFETs

2007 International Workshop on Electron Devices and Semiconductor Technology (EDST), 2007, p.31-36

2007

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Optimization of a foundry compatible 0.18 /spl mu/m CMOS RF and mixed single process

ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575), 2002, p.419-423

2002

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Towards Unification of MOS Compact Models with the Unified Regional Approach

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, 2006, p.1193-1197

2006

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Rigorous Surface-Potential Solution for Undoped Symmetric Double-Gate MOSFETs Considering Both Electrons and Holes at Quasi NonEquilibrium

A Compact Model for Undoped Silicon-Nanowire MOSFETs With Schottky-Barrier Source/Drain

"Ground-Referenced" Model for Three-Terminal Symmetric Double-Gate MOSFETs With Source/Drain Symmetry

A Compact Model Satisfying Gummel Symmetry in Higher Order Derivatives and Applicable to Asymmetric MOSFETs

A New Impact-Ionization Current Model Applicable to Both Bulk and SOI MOSFETs by Considering Self-Lattice-Heating

Under-Bump Metallization Contact Resistance ( R ) Characterization at 10- \mu \text Polymer Passivation Opening

Physics-based single-piece charge model for strained-Si MOSFETs

Surface-Potential Solution for Generic Undoped MOSFETs With Two Gates

Implicit Analytical Surface/Interface Potential Solutions for Modeling Strained-Si MOSFETs

Effect of substrate doping on the capacitance-Voltage characteristics of strained-silicon pMOSFETs

Subcircuit Compact Model for Dopant-Segregated Schottky Gate-All-Around Si-Nanowire MOSFETs

Explicit Compact Surface-Potential and Drain-Current Models for Generic Asymmetric Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistors

Fine-Pitch RDL Integration for Fan-Out Wafer-Level Packaging

Evaluation on multiple layer PBO-based Cu RDL process for Fan-Out Wafer Level Packaging (FOWLP)

aGround-Referenceda Model for Three-Terminal Symmetric Double-Gate MOSFETs With Source/Drain Symmetry

Extraction of physical parameters of strained silicon MOSFETs from C-V measurement

Unification of MOS compact models with the unified regional modeling approach

Unification of MOS compact models with the unified regional modeling approach : Computational Electronics in Asia and Selected Papers from IWCE 2009 in Beijing

Unified regional modeling approach to emerging multiple-gate/nanowire MOSFETs

Unified compact modeling for Bulk/SOI/FinFET/SiNW MOSFETs

RF spiral planar inductor designs - preliminary results [RFIC applications]

A new impact ionization current model applicable to both bulk and SOI MOSFETs by considering self-lattice-heating

Unified Compact Modeling of Emerging Multiple-Gate MOSFETs

Optimization of a foundry compatible 0.18 /spl mu/m CMOS RF and mixed single process

Towards Unification of MOS Compact Models with the Unified Regional Approach

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