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Evaluation of Single Event Upset Mitigation Schemes for SRAM based FPGAs using the FLIPPER Fault Injection Platform

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007, p.105-113

2007

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Using FLIPPER to Predict Proton Irradiation Results for VIRTEX 2 Devices: A Case Study

IEEE transactions on nuclear science, 2009-08, Vol.56 (4), p.2103-2110

2009

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Particle identification via pulse shape analysis for large-area silicon detectors of the CHIMERA array

IEEE transactions on nuclear science, 2005-10, Vol.52 (5), p.1624-1629

2005

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SEU sensitivity of virtex configuration logic

IEEE transactions on nuclear science, 2005-12, Vol.52 (6), p.2462-2467

2005

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CHIMERA data acquisition via digital sampling technique

IEEE transactions on nuclear science, 2004-08, Vol.51 (4), p.1475-1481

2004

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PRESTO: a computational and storage unit for CHIMERA DAQ

IEEE transactions on nuclear science, 2005-10, Vol.52 (5), p.1673-1678

2005

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CHIMERA data acquisition and computational system using DSP-based VME modules

IEEE transactions on nuclear science, 2002-04, Vol.49 (2), p.432-436

2002

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Processing CsI(Tl) 2-D matrices by means of neural networks and Markov random fields

IEEE transactions on nuclear science, 2002-08, Vol.49 (4), p.1661-1668

2002

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MUSE: an integrated trigger and readout control system for CHIMERA

IEEE transactions on nuclear science, 2002-04, Vol.49 (2), p.334-338

2002

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A fault-tolerance strategy for an FPGA-based multi-stage interconnection network in a multi-sensor system for space application

Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2001, p.191-199

2001

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Massively parallel systems

Journal of systems architecture, 1997-04, Vol.43 (6), p.371-372

Sechi, G.R.

1997

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A tool for injecting SEU-like faults into the configuration control mechanism of Xilinx Virtex FPGAs

Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems, 2003, p.71-78

2003

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A spatial density analysis technique for the automatic classification of 4/spl pi/ detector data

IEEE transactions on nuclear science, 2001-06, Vol.48 (3), p.385-390

2001

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A spatial density analysis technique for the automatic classification of 4[pi] detector data

IEEE transactions on nuclear science, 2001-06, Vol.48 (3), p.385

2001

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Fault-tolerant voting mechanism and recovery scheme for TMR FPGA-based systems

Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223), 1998, p.233-240

1998

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Achieving fault-tolerance by shifted and rotated operands in TMR non-diverse ALUs

Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2000, p.155-163

2000

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A fault injection tool for SRAM-based FPGAs

9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003, 2003, p.129-133

2003

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Implementing a self-checking neural system for photon event identification by SRAM-based FPGAs

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99), 1999, p.274-282

1999

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A model of a microprogrammed functional-oriented computing unit

[1990] Proceedings of the 23rd Annual Workshop and Symposium@m_MICRO 23: Microprogramming and Microarchitecture, 1990, p.292-298

1990

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KITE: a behavioural approach to fault-tolerance in FPGA-based systems

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 1996, p.327-334

1996

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Heavy ion effects on configuration logic of Virtex FPGAs

11th IEEE International On-Line Testing Symposium, 2005, p.49-53

2005

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A fault-tolerant FPGA-based multi-stage interconnection network for space applications

Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002, 2002, p.302-306

2002

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A Fault-Tolerance Scheme for a MIN-Based Multi-Sensor System

The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01), 2001, p.130-136

2001

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Radiation test methodology for SRAM-based FPGAs by using THESIC

9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003, 2003, p.162

2003

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Novel fault-tolerant adder design for FPGA-based systems

Proceedings Seventh International On-Line Testing Workshop, 2001, p.54-58

2001

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Evaluation of Single Event Upset Mitigation Schemes for SRAM based FPGAs using the FLIPPER Fault Injection Platform

Using FLIPPER to Predict Proton Irradiation Results for VIRTEX 2 Devices: A Case Study

Particle identification via pulse shape analysis for large-area silicon detectors of the CHIMERA array

SEU sensitivity of virtex configuration logic

CHIMERA data acquisition via digital sampling technique

PRESTO: a computational and storage unit for CHIMERA DAQ

CHIMERA data acquisition and computational system using DSP-based VME modules

Processing CsI(Tl) 2-D matrices by means of neural networks and Markov random fields

MUSE: an integrated trigger and readout control system for CHIMERA

A fault-tolerance strategy for an FPGA-based multi-stage interconnection network in a multi-sensor system for space application

Massively parallel systems

A tool for injecting SEU-like faults into the configuration control mechanism of Xilinx Virtex FPGAs

A spatial density analysis technique for the automatic classification of 4/spl pi/ detector data

A spatial density analysis technique for the automatic classification of 4[pi] detector data

Fault-tolerant voting mechanism and recovery scheme for TMR FPGA-based systems

Achieving fault-tolerance by shifted and rotated operands in TMR non-diverse ALUs

A fault injection tool for SRAM-based FPGAs

Implementing a self-checking neural system for photon event identification by SRAM-based FPGAs

A model of a microprogrammed functional-oriented computing unit

KITE: a behavioural approach to fault-tolerance in FPGA-based systems

Heavy ion effects on configuration logic of Virtex FPGAs

A fault-tolerant FPGA-based multi-stage interconnection network for space applications

A Fault-Tolerance Scheme for a MIN-Based Multi-Sensor System

Radiation test methodology for SRAM-based FPGAs by using THESIC

Novel fault-tolerant adder design for FPGA-based systems

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