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Origin of the threshold voltage instability in SiO2/HfO2 dual layer gate dielectrics

IEEE electron device letters, 2003-02, Vol.24 (2), p.87-89

2003

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IEEE_Xplore

CMOS without doping: Multi-gate silicon-nanowire field-effect-transistors

Solid-state electronics, 2012-04, Vol.70, p.33-38

2012

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Virtually dopant-free CMOS: Midgap Schottky-barrier nanowire field-effect-transistors for high temperature applications

Solid-state electronics, 2012-08, Vol.74, p.91-96

2012

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On the effects of solution and reaction parameters for the aerosol-assisted CVD growth of long carbon nanotubes

Applied physics. A, Materials science & processing, 2006-03, Vol.82 (4), p.719-725

2006

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Charge trapping in SiO2/HfO2 gate dielectrics: Comparison between charge-pumping and pulsed ID-VG

Microelectronic engineering, 2004-04, Vol.72 (1-4), p.267-272

2004

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Stress induced charge trapping effects in SiO2/Al2O3 gate stacks with TiN electrodes

Journal of applied physics, 2003-11, Vol.94 (10), p.6627-6630

2003

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Large-Scale In Situ Fabrication of Voltage-Programmable Dual-Layer High-[Formula Omitted] Dielectric Carbon Nanotube Memory Devices With High On/Off Ratio

IEEE electron device letters, 2008-12, Vol.29 (12), p.1349

2008

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Large-Scale In Situ Fabrication of Voltage-Programmable Dual-Layer High- \kappa Dielectric Carbon Nanotube Memory Devices With High On/Off Ratio

IEEE electron device letters, 2008-12, Vol.29 (12), p.1349-1352

2008

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IEEE_Xplore

Introduction of crystalline high- k gate dielectrics in a CMOS process

Journal of non-crystalline solids, 2005-07, Vol.351 (21), p.1885-1889

2005

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PMMA-enhancement of the lateral growth of transfer-free in situ CCVD grown graphene

2016 13th International Multi-Conference on Systems, Signals & Devices (SSD), 2016, p.458-551

2016

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Virtually dopant-free CMOS: Midgap Schottky-barrier nanowire field-effect-transistors for high temperature applications: Selected Papers from the ESSDERC 2011 Conference

Solid-state electronics, 2012, Vol.74, p.91-96

2012

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Investigation of transfer-free catalytic CVD graphene on SiO2 by means of conductive atomic force microscopy

2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS), 2016, p.1-4

2016

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Alternative Optimization Techniques for Shallow Trench Isolation and Replacement Gate Technology Chemical Mechanical Planarization

Transactions on Electrical and Electronic Materials, 2007, 8(1), , pp.1-4

2007

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EXTIGATE: The ultimate process architecture for submicron CMOS technologies

IEEE transactions on electron devices, 1997-11, Vol.44 (11), p.2070-2077

1997

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IEEE_Xplore

Through-the-gate-implanted ultrathin gate oxide MOSFET's with corner parasitics-free shallow-trench-isolation

IEEE electron device letters, 1999-07, Vol.20 (7), p.363-365

1999

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IEEE_Xplore

Process integration and nanometer-scale electrical characterization of crystalline high- k gate dielectrics

Microelectronics and reliability, 2005-05, Vol.45 (5), p.790-793

2005

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Reliability issues and length dependence of nanocrystalline graphene field-effect transistors for gas sensing

2019 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS), 2019, p.1-5

2019

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Evidence for spatial distribution of traps in MOS systems after fowler nordheim stress

Microelectronic engineering, 1999, Vol.48 (1), p.147-150

1999

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Electrical characterisation of crystalline praseodymium oxide high-k gate dielectric MOSFETs

ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003, 2003, p.243-246

2003

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IEEE_Xplore

Charge trapping and dielectric reliability of SiO2-Al2O3 gate stacks with TiN electrodes

IEEE transactions on electron devices, 2003-05, Vol.50 (5), p.1261

2003

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Ammonia sensors based on in situ fabricated nanocrystalline graphene field-effect devices

2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS), 2018, p.1-5

2018

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Corner-parasitics-free low-cost trench isolation

IEEE electron device letters, 1999-11, Vol.20 (11), p.563-565

1999

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IEEE_Xplore

Progress in device isolation technology

Microelectronics and reliability, 2001-04, Vol.41 (4), p.483-490

Schwalke, Udo

2001

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CMOS without doping: Midgap Schottky-barrier nanowire field-effect-transistors for high-temperature applications

2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2011, p.263-266

2011

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IEEE_Xplore

Ultra-thick gate oxides: charge generation and its impact on reliability

Microelectronics and reliability, 2001-07, Vol.41 (7), p.1007-1010

2001

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Origin of the threshold voltage instability in SiO2/HfO2 dual layer gate dielectrics

CMOS without doping: Multi-gate silicon-nanowire field-effect-transistors

Virtually dopant-free CMOS: Midgap Schottky-barrier nanowire field-effect-transistors for high temperature applications

On the effects of solution and reaction parameters for the aerosol-assisted CVD growth of long carbon nanotubes

Charge trapping in SiO2/HfO2 gate dielectrics: Comparison between charge-pumping and pulsed ID-VG

Stress induced charge trapping effects in SiO2/Al2O3 gate stacks with TiN electrodes

Large-Scale In Situ Fabrication of Voltage-Programmable Dual-Layer High-[Formula Omitted] Dielectric Carbon Nanotube Memory Devices With High On/Off Ratio

Large-Scale In Situ Fabrication of Voltage-Programmable Dual-Layer High- \kappa Dielectric Carbon Nanotube Memory Devices With High On/Off Ratio

Introduction of crystalline high- k gate dielectrics in a CMOS process

PMMA-enhancement of the lateral growth of transfer-free in situ CCVD grown graphene

Virtually dopant-free CMOS: Midgap Schottky-barrier nanowire field-effect-transistors for high temperature applications: Selected Papers from the ESSDERC 2011 Conference

Investigation of transfer-free catalytic CVD graphene on SiO2 by means of conductive atomic force microscopy

Alternative Optimization Techniques for Shallow Trench Isolation and Replacement Gate Technology Chemical Mechanical Planarization

EXTIGATE: The ultimate process architecture for submicron CMOS technologies

Through-the-gate-implanted ultrathin gate oxide MOSFET's with corner parasitics-free shallow-trench-isolation

Process integration and nanometer-scale electrical characterization of crystalline high- k gate dielectrics

Reliability issues and length dependence of nanocrystalline graphene field-effect transistors for gas sensing

Evidence for spatial distribution of traps in MOS systems after fowler nordheim stress

Electrical characterisation of crystalline praseodymium oxide high-k gate dielectric MOSFETs

Charge trapping and dielectric reliability of SiO2-Al2O3 gate stacks with TiN electrodes

Ammonia sensors based on in situ fabricated nanocrystalline graphene field-effect devices

Corner-parasitics-free low-cost trench isolation

Progress in device isolation technology

CMOS without doping: Midgap Schottky-barrier nanowire field-effect-transistors for high-temperature applications

Ultra-thick gate oxides: charge generation and its impact on reliability

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