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A 22-gb/s PAM-4 receiver in 90-nm CMOS SOI technology

IEEE journal of solid-state circuits, 2006-04, Vol.41 (4), p.954-965

2006

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LC PLL With 1.2-Octave Locking Range Based on Mutual-Inductance Switching in 45-nm SOI CMOS

IEEE journal of solid-state circuits, 2009-02, Vol.44 (2), p.436-449

2009

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30-40-GHz drain-pumped passive-mixer MMIC fabricated on VLSI SOI CMOS technology

IEEE transactions on microwave theory and techniques, 2004-05, Vol.52 (5), p.1382-1391

2004

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A 1.25-5 GHz Clock Generator With High-Bandwidth Supply-Rejection Using a Regulated-Replica Regulator in 45-nm CMOS

IEEE journal of solid-state circuits, 2009-11, Vol.44 (11), p.2901-2910

2009

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Switched Inductor With Wide Tuning Range and Small Inductance Step Sizes

IEEE microwave and wireless components letters, 2009-08, Vol.19 (8), p.515-517

2009

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A 100-mW 4×10 Gb/s transceiver in 80-nm CMOS for high-density optical interconnects

IEEE journal of solid-state circuits, 2005-12, Vol.40 (12), p.2667

2005

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A nonlinear microwave MOSFET model for SPICE simulators

IEEE transactions on microwave theory and techniques, 1998-05, Vol.46 (5), p.604-610

1998

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Novel design topology for ultra low power down converters with broadband on chip matching network

IEEE transactions on microwave theory and techniques, 1995-12, Vol.43 (12), p.2946-2951

1995

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Jitter measurements of high-speed serial links

IEEE design & test of computers, 2004-11, Vol.21 (6), p.536-543

2004

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A 100-mW 4/spl times/10 Gb/s transceiver in 80-nm CMOS for high-density optical interconnects

IEEE journal of solid-state circuits, 2005-12, Vol.40 (12), p.2667-2679

2005

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A 0.94-ps-RMS-jitter 0.016-mm/sup 2/ 2.5-GHz multiphase generator PLL with 360/spl deg/ digitally programmable phase shift for 10-Gb/s serial links

IEEE journal of solid-state circuits, 2005-12, Vol.40 (12), p.2700-2712

2005

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A low-power 20-GHz 52-dB/spl Omega/ transimpedance amplifier in 80-nm CMOS

IEEE journal of solid-state circuits, 2004-06, Vol.39 (6), p.885-894

2004

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A low-power 20-GHz 52-dB[Omega] transimpedance amplifier in 80-nm CMOS

IEEE journal of solid-state circuits, 2004-06, Vol.39 (6), p.885

2004

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A 0.94-ps-RMS-jitter 0.016-mm2 2.5-GHz multiphase generator PLL with 360° digitally programmable phase shift for 10-Gb/s serial links

IEEE journal of solid-state circuits, 2005-12, Vol.40 (12), p.2700-2712

2005

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A 40-Gb/s, digitally programmable peaking limiting amplifier with 20-dB differential gain in 90-nm CMOS

IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006, 2006, p.4 pp.

2006

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A DC-to-44-GHz 19dB Gain Amplifier in 90nm CMOS Using Capacitive Bandwidth Enhancement

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, 2006, p.2082-2091

2006

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78-dB shot-noise limited optical low-coherence reflectometry at 42-m/s scan speed

IEEE photonics technology letters, 1997-12, Vol.9 (12), p.1613-1615

1997

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Design and implementation of an optical interconnect demonstrator with board-integrated waveguides and microlens coupling

Digest of the LEOS Summer Topical Meetings Biophotonics/Optical Interconnects and VLSI Photonics/WBM Microcavities, 2004, 2004, p.19-20

2004

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Broadband noise parameter and S-parameter measurement technique

1997 IEEE MTT-S International Microwave Symposium Digest, 1997, Vol.3, p.1443-1446 vol.3

1997

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Technology independent degradation of minimum noise figure due to pad parasitics

1998 IEEE MTT-S International Microwave Symposium Digest (Cat. No.98CH36192), 1998, Vol.1, p.145-148 vol.1

1998

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Novel design topology for ultra low power down converters with broadband on chip matching network

Proceedings of 1995 IEEE MTT-S International Microwave Symposium, 1995, p.1329-1332 vol.3

Schmatz, M.L.

1995

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Improvements on a MOSFET model for non-linear RF simulations

1997 IEEE MTT-S International Microwave Symposium Digest, 1997, Vol.2, p.865-868 vol.2

1997

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High-speed and high-density chip-to-chip interconnections: trends and techniques

IEEE 9th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.00TH8524), 2000, p.23-24

Schmatz, M.L.

2000

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Effect of body contacts on high-speed circuits in 90 nm CMOS SOI technology

International Symposium on Signals, Circuits and Systems, 2005. ISSCS 2005, 2005, Vol.2, p.537-540 Vol. 2

2005

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2 GHz monolithic low noise amplifier using lower than 1 V supply voltage

Proceedings of 1997 Wireless Communications Conference, 1997, p.138-140

1997

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A 22-gb/s PAM-4 receiver in 90-nm CMOS SOI technology

LC PLL With 1.2-Octave Locking Range Based on Mutual-Inductance Switching in 45-nm SOI CMOS

30-40-GHz drain-pumped passive-mixer MMIC fabricated on VLSI SOI CMOS technology

A 1.25-5 GHz Clock Generator With High-Bandwidth Supply-Rejection Using a Regulated-Replica Regulator in 45-nm CMOS

Switched Inductor With Wide Tuning Range and Small Inductance Step Sizes

A 100-mW 4×10 Gb/s transceiver in 80-nm CMOS for high-density optical interconnects

A nonlinear microwave MOSFET model for SPICE simulators

Novel design topology for ultra low power down converters with broadband on chip matching network

Jitter measurements of high-speed serial links

A 100-mW 4/spl times/10 Gb/s transceiver in 80-nm CMOS for high-density optical interconnects

A 0.94-ps-RMS-jitter 0.016-mm/sup 2/ 2.5-GHz multiphase generator PLL with 360/spl deg/ digitally programmable phase shift for 10-Gb/s serial links

A low-power 20-GHz 52-dB/spl Omega/ transimpedance amplifier in 80-nm CMOS

A low-power 20-GHz 52-dB[Omega] transimpedance amplifier in 80-nm CMOS

A 0.94-ps-RMS-jitter 0.016-mm2 2.5-GHz multiphase generator PLL with 360° digitally programmable phase shift for 10-Gb/s serial links

A 40-Gb/s, digitally programmable peaking limiting amplifier with 20-dB differential gain in 90-nm CMOS

A DC-to-44-GHz 19dB Gain Amplifier in 90nm CMOS Using Capacitive Bandwidth Enhancement

78-dB shot-noise limited optical low-coherence reflectometry at 42-m/s scan speed

Design and implementation of an optical interconnect demonstrator with board-integrated waveguides and microlens coupling

Broadband noise parameter and S-parameter measurement technique

Technology independent degradation of minimum noise figure due to pad parasitics

Novel design topology for ultra low power down converters with broadband on chip matching network

Improvements on a MOSFET model for non-linear RF simulations

High-speed and high-density chip-to-chip interconnections: trends and techniques

Effect of body contacts on high-speed circuits in 90 nm CMOS SOI technology

2 GHz monolithic low noise amplifier using lower than 1 V supply voltage

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