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Cell-Aware Test

IEEE transactions on computer-aided design of integrated circuits and systems, 2014-09, Vol.33 (9), p.1396-1409

2014

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MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics

Journal of electronic testing, 2010-06, Vol.26 (3), p.307-322

2010

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On Acceleration of SAT-Based ATPG for Industrial Designs

IEEE transactions on computer-aided design of integrated circuits and systems, 2008-07, Vol.27 (7), p.1329-1333

2008

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A 4 x 4 x 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links

IEEE journal of solid-state circuits, 2017-01, Vol.52 (1), p.33-49

2017

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A 4 \times 4 \times 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links

IEEE journal of solid-state circuits, 2017-01, Vol.52 (1), p.33-49

2017

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SUPERB: Simulator utilizing parallel evaluation of resistive bridges

ACM transactions on design automation of electronic systems, 2009-08, Vol.14 (4), p.1-21

2009

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Restrict Encoding for Mixed-Mode BIST

2009 27th IEEE VLSI Test Symposium, 2009, p.179-184

2009

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Resistive Bridging Fault Simulation of Industrial Circuits

2008 Design, Automation and Test in Europe, 2008, p.628-633

2008

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IJTAG supported 3D DFT using chiplet-footprints for testing multi-chips active interposer system

2016 21th IEEE European Test Symposium (ETS), 2016, p.1-6

2016

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Fault detection and diagnosis with parity trees for space compaction of test responses

2006 43rd ACM/IEEE Design Automation Conference, 2006, p.1095-1098

2006

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Programmable deterministic Built-In Self-Test

2007 IEEE International Test Conference, 2007, p.1-9

2007

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ABCD modeling of crosstalk coupling noise to analyze the signal integrity losses on the victim interconnect in DSM chips

18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design, 2005, p.354-359

2005

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3D DFT Challenges and Solutions

2015 IEEE Computer Society Annual Symposium on VLSI, 2015, p.603-608

2015

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Modeling and analysis of crosstalk coupling effect on the victim interconnect using the ABCD network model

19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings, 2004, p.174-182

2004

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A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips

14th Asian Test Symposium (ATS'05), 2005, p.22-27

2005

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2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures

2014 IEEE Computer Society Annual Symposium on VLSI, 2014, p.386-391

2014

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Gate-Exhaustive and Cell-Aware pattern sets for industrial designs

Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, 2011, p.1-4

2011

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Resistive bridging fault simulation of industrial circuits

Proceedings of the conference on Design, automation and test in Europe, 2008, p.628-633

2008

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Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs

2010 15th IEEE European Test Symposium, 2010, p.176-181

2010

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Computation and Application of Absolute Dominators in Industrial Designs

12th IEEE European Test Symposium (ETS'07), 2007, p.137-144

2007

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Deterministic Logic BIST for Transition Fault Testing

Eleventh IEEE European Test Symposium (ETS'06), 2006, p.123-130

2006

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Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults

2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007), 2007, p.181-187

2007

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Analysis of crosstalk coupling effects between aggressor and victim interconnect using two-port network model

Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects, 2004, p.81-84

2004

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Cell-Aware Test

MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics

On Acceleration of SAT-Based ATPG for Industrial Designs

A 4 x 4 x 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links

A 4 \times 4 \times 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links

SUPERB: Simulator utilizing parallel evaluation of resistive bridges

Restrict Encoding for Mixed-Mode BIST

Resistive Bridging Fault Simulation of Industrial Circuits

IJTAG supported 3D DFT using chiplet-footprints for testing multi-chips active interposer system

Fault detection and diagnosis with parity trees for space compaction of test responses

Programmable deterministic Built-In Self-Test

ABCD modeling of crosstalk coupling noise to analyze the signal integrity losses on the victim interconnect in DSM chips

3D DFT Challenges and Solutions

Modeling and analysis of crosstalk coupling effect on the victim interconnect using the ABCD network model

A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips

2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures

Gate-Exhaustive and Cell-Aware pattern sets for industrial designs

Resistive bridging fault simulation of industrial circuits

Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs

Computation and Application of Absolute Dominators in Industrial Designs

Deterministic Logic BIST for Transition Fault Testing

Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults

Analysis of crosstalk coupling effects between aggressor and victim interconnect using two-port network model

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