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Biopsychosocial impact of voicing and general coping style in teachers

Folia phoniatrica et logopaedica, 2010-01, Vol.62 (1-2), p.40-46

2010

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Switching mechanism in two-terminal vanadium dioxide devices

Nanotechnology, 2015-04, Vol.26 (16), p.165202-165202

2015

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The VO2 interface, the metal-insulator transition tunnel junction, and the metal-insulator transition switch On-Off resistance

Journal of applied physics, 2012-12, Vol.112 (12)

2012

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High- k dielectrics for future generation memory devices (Invited Paper)

Microelectronic engineering, 2009-07, Vol.86 (7), p.1789-1795

2009

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Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect

2015 Symposium on VLSI Technology (VLSI Technology), 2015, p.T56-T57

2015

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Low temperature chemical vapour synthesis of Cu3Ge thin films for interconnect applications

Microelectronic engineering, 2014-05, Vol.120, p.246-250

2014

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(Invited) Probing the Intrinsic Limitations of the Contact Resistance of Metal/Semiconductor Interfaces through Atomistic Simulations

ECS transactions, 2017, Vol.80 (1), p.303-311

2017

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A Conformal Oxide Liner for Through Silicon Vias by Pulsed SA-CVD Deposition

ECS transactions, 2009, Vol.25 (8), p.659-666

2009

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Study of the Intrinsic Limitations of the Contact Resistance of Metal/Semiconductor Interfaces through Atomistic Simulations

ECS journal of solid state science and technology, 2018, Vol.7 (6), p.N73-N80

2018

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Ultralow-resistivity CMOS contact scheme with pre-contact amorphization plus Ti (germano-)silicidation

2016 IEEE Symposium on VLSI Technology, 2016, p.1-2

2016

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Review of Silicon Nanowire Oxidation

ECS transactions, 2011, Vol.34 (1), p.535-540

2011

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Low temperature chemical vapour synthesis of Cu sub(3)Ge thin films for interconnect applications

Microelectronic engineering, 2014-05, Vol.120, p.246-250

2014

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Scalability of plasma enhanced atomic layer deposited ruthenium films for interconnect applications

Journal of vacuum science & technology. A, Vacuum, surfaces, and films, 2012-01, Vol.30 (1), p.01A103-01A103-6

2012

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Direct physical evidence of mechanisms of leakage and equivalent oxide thickness reduction in metal-insulator-metal capacitors based on RuO x /TiO x /Sr x Ti y O z /TiN stacks

Applied physics letters, 2012-07, Vol.101 (4), p.42901

2012

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ALD Ru and its Application in DRAM MIM-Capacitors and Interconnect

ECS transactions, 2011, Vol.34 (1), p.509-514

2011

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Metal-Organic Chemical Vapor Deposition of Ti-Doped NiO Layers for Application in Resistive Switching Memories

ECS transactions, 2010, Vol.33 (3), p.313-322

2010

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Sub-10−9 Ω·cm2 contact resistivity on p-SiGe achieved by Ga doping and nanosecond laser activation

2017 Symposium on VLSI Technology, 2017, p.T214-T215

2017

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Cost-effective cleaning and high-quality thin gate oxides

IBM journal of research and development, 1999-05, Vol.43 (3), p.339-350

1999

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(Invited) Plasma Enhanced Atomic Layer Deposited Ruthenium for MIMCAP Applications

ECS transactions, 2011, Vol.41 (2), p.41-51

2011

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High-@@ik@ dielectrics for future generation memory devices (Invited Paper)

Microelectronic engineering, 2009-09, Vol.86 (7-9), p.1789-1795

2009

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Quantitative Analysis of Trace Metals in Silicon Nitride Films by a Vapor Phase Decomposition/Solution Collection Approach

Journal of the Electrochemical Society, 2000-01, Vol.147 (4), p.1499

2000

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Characterisation and integration feasibility of JSR’s low- k dielectric LKD-5109

Microelectronic engineering, 2002-10, Vol.64 (1), p.25-33

2002

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Towards 1X DRAM: Improved leakage 0.4 nm EOT STO-based MIMcap and explanation of leakage reduction mechanism showing further potential

2011 Symposium on VLSI Technology - Digest of Technical Papers, 2011, p.168-169

2011

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Sandwich stacks replacing SiO2 in standard bonded Si-on-Insulator (SOI) substrates to obtain a high-thermal conductivity HTC-SOI substrate

2008 IEEE International SOI Conference, 2008, p.67-68

2008

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Biopsychosocial impact of voicing and general coping style in teachers

Switching mechanism in two-terminal vanadium dioxide devices

The VO2 interface, the metal-insulator transition tunnel junction, and the metal-insulator transition switch On-Off resistance

High- k dielectrics for future generation memory devices (Invited Paper)

Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect

Low temperature chemical vapour synthesis of Cu3Ge thin films for interconnect applications

(Invited) Probing the Intrinsic Limitations of the Contact Resistance of Metal/Semiconductor Interfaces through Atomistic Simulations

A Conformal Oxide Liner for Through Silicon Vias by Pulsed SA-CVD Deposition

Study of the Intrinsic Limitations of the Contact Resistance of Metal/Semiconductor Interfaces through Atomistic Simulations

Ultralow-resistivity CMOS contact scheme with pre-contact amorphization plus Ti (germano-)silicidation

Review of Silicon Nanowire Oxidation

Low temperature chemical vapour synthesis of Cu sub(3)Ge thin films for interconnect applications

Scalability of plasma enhanced atomic layer deposited ruthenium films for interconnect applications

Direct physical evidence of mechanisms of leakage and equivalent oxide thickness reduction in metal-insulator-metal capacitors based on RuO x /TiO x /Sr x Ti y O z /TiN stacks

ALD Ru and its Application in DRAM MIM-Capacitors and Interconnect

Metal-Organic Chemical Vapor Deposition of Ti-Doped NiO Layers for Application in Resistive Switching Memories

Sub-10−9 Ω·cm2 contact resistivity on p-SiGe achieved by Ga doping and nanosecond laser activation

Cost-effective cleaning and high-quality thin gate oxides

(Invited) Plasma Enhanced Atomic Layer Deposited Ruthenium for MIMCAP Applications

High-@@ik@ dielectrics for future generation memory devices (Invited Paper)

Quantitative Analysis of Trace Metals in Silicon Nitride Films by a Vapor Phase Decomposition/Solution Collection Approach

Characterisation and integration feasibility of JSR’s low- k dielectric LKD-5109

Towards 1X DRAM: Improved leakage 0.4 nm EOT STO-based MIMcap and explanation of leakage reduction mechanism showing further potential

Sandwich stacks replacing SiO2 in standard bonded Si-on-Insulator (SOI) substrates to obtain a high-thermal conductivity HTC-SOI substrate

High-k Dielectrics and Metal Gates for Future Generation Memory Devices

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