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Discrete-time battery models for system-level low-power design

IEEE transactions on very large scale integration (VLSI) systems, 2001-10, Vol.9 (5), p.630-640

2001

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Architectures and synthesis algorithms for power-efficient bus interfaces

IEEE transactions on computer-aided design of integrated circuits and systems, 2000-09, Vol.19 (9), p.969-980

2000

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The bulk shipping business: market cycles and shipowners' biases

Maritime policy and management, 2007-12, Vol.34 (6), p.577-590

Scarsi, Roberta

2007

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Scheduling battery usage in mobile systems

IEEE transactions on very large scale integration (VLSI) systems, 2003-12, Vol.11 (6), p.1136-1143

2003

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Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers

ACM transactions on design automation of electronic systems, 1999-10, Vol.4 (4), p.351-375

1999

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Synthesis of low-overhead interfaces for power-efficient communication over wide buses

Proceedings - ACM IEEE Design Automation Conference, 1999, p.128-133

1999

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Glitch power minimization by selective gate freezing

IEEE transactions on very large scale integration (VLSI) systems, 2000-06, Vol.8 (3), p.287-298

2000

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Extending lifetime of portable systems by battery scheduling

Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, 2001, p.197-201

2001

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Stream synthesis for efficient power simulation based on spectral transforms

IEEE transactions on very large scale integration (VLSI) systems, 2001-06, Vol.9 (3), p.417-426

2001

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A multilevel engine for fast power simulation of realistic input streams

IEEE transactions on computer-aided design of integrated circuits and systems, 2000-04, Vol.19 (4), p.459-472

2000

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Battery-driven dynamic power management

IEEE design & test of computers, 2001-03, Vol.18 (2), p.53-60

2001

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A comparative study of complexity-based capacitance macro-models

Conference Record of Thirty-Second Asilomar Conference on Signals, Systems and Computers (Cat. No.98CH36284), 1998, Vol.2, p.1038-1041 vol.2

1998

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Glitch power minimization by gate freezing

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078), 1999, p.163-167

1999

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A discrete-time battery model for high-level power estimation

Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537), 2000, p.35-39

2000

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F-gate: a device for glitch power minimization

Conference Record of Thirty-Second Asilomar Conference on Signals, Systems and Computers (Cat. No.98CH36284), 1998, Vol.2, p.1047-1051 vol.2

1998

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Quick generation of temporal power waveforms for RT-level hard macros

1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon, 1997, p.331-337

1997

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On the benefits of kernel extraction during logic optimization

2000 10th Mediterranean Electrotechnical Conference. Information Technology and Electrotechnology for the Mediterranean Countries. Proceedings. MeleCon 2000 (Cat. No.00CH37099), 2000, Vol.1, p.53-56 vol.1

2000

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