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SAT-Hard Cyclic Logic Obfuscation for Protecting the IP in the Manufacturing Supply Chain

IEEE transactions on very large scale integration (VLSI) systems, 2020-04, Vol.28 (4), p.954-967

2020

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IEEE_Xplore

Optimized and Automated Secure IC Design Flow: A Defense-in-Depth Approach

IEEE transactions on circuits and systems. I, Regular papers, 2024-05, Vol.71 (5), p.2031-2044

2024

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IEEE_Xplore

Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits

IEEE transactions on very large scale integration (VLSI) systems, 2021-04, Vol.29 (4), p.643-656

2021

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IEEE_Xplore

From Cryptography to Logic Locking: A Survey on the Architecture Evolution of Secure Scan Chains

IEEE access, 2021, Vol.9, p.73133-73151

2021

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AVATAR: NN-Assisted Variation Aware Timing Analysis & Reporting for Hardware Trojan Detection

IEEE access, 2021-01, Vol.9, p.1-1

2021

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Enabling Micro AI for Securing Edge Devices at Hardware Level

IEEE journal on emerging and selected topics in circuits and systems, 2021-12, Vol.11 (4), p.803-815

2021

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IEEE_Xplore

Cognitive and Scalable Technique for Securing IoT Networks Against Malware Epidemics

IEEE access, 2020-01, Vol.8, p.1-1

2020

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Advanced Reinforcement Learning Solution for Clock Skew Engineering: Modified Q-Table Update Technique for Peak Current and IR Drop Minimization

IEEE access, 2023, Vol.11, p.87869-87886

2023

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Hardware Accelerated Mappers for Hadoop MapReduce Streaming

IEEE transactions on multi-scale computing systems, 2018-10, Vol.4 (4), p.734-748

2018

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IEEE_Xplore

Analyzing hardware based malware detectors

2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), 2017, p.1-6

2017

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ICNN: The Iterative Convolutional Neural Network

ACM transactions on embedded computing systems, 2020-01, Vol.18 (6), p.1-27

2020

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MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits

IEEE transactions on very large scale integration (VLSI) systems, 2011-12, Vol.19 (12), p.2303-2316

2011

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IEEE_Xplore

Full-Lock: Hard Distributions of SAT instances for Obfuscating Circuits using Fully Configurable Logic and Routing Blocks

2019 56th ACM/IEEE Design Automation Conference (DAC), 2019, p.1-6

2019

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A Low Power JPEG2000 Encoder With Iterative and Fault Tolerant Error Concealment

IEEE transactions on very large scale integration (VLSI) systems, 2009-06, Vol.17 (6), p.827-837

2009

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IEEE_Xplore

InterLock: an intercorrelated logic and routing locking

2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020, p.1-9

2020

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IEEE_Xplore

NNgSAT: neural network guided SAT attack on logic locked complex structures

2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020, p.1-9

2020

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IEEE_Xplore

ICNN: An iterative implementation of convolutional neural networks to enable energy and computational complexity aware dynamic approximation

2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, p.551-556

2018

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IEEE_Xplore

Machine Learning-Based Approaches for Energy-Efficiency Prediction and Scheduling in Composite Cores Architectures

2017 IEEE International Conference on Computer Design (ICCD), 2017, p.129-136

2017

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IEEE_Xplore

Hybrid-shield: accurate and efficient cross-layer countermeasure for run-time detection and mitigation of cache-based side-channel attacks

2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020, p.1-9

2020

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IEEE_Xplore

Ensemble learning for effective run-time hardware-based malware detection: a comprehensive analysis and classification

Proceedings of the 55th Annual Design Automation Conference, 2018, p.1-6

2018

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Energy-efficient acceleration of MapReduce applications using FPGAs

Journal of parallel and distributed computing, 2018-09, Vol.119, p.1-17

2018

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Phased-Guard: Multi-Phase Machine Learning Framework for Detection and Identification of Zero-Day Microarchitectural Side-Channel Attacks

2020 IEEE 38th International Conference on Computer Design (ICCD), 2020, p.648-655

2020

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IEEE_Xplore

2SMaRT: A Two-Stage Machine Learning-Based Approach for Run-Time Specialized Hardware-Assisted Malware Detection

2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, p.728-733

2019

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IEEE_Xplore

Breaking the Design and Security Trade-off of Look-up-table–based Obfuscation

ACM transactions on design automation of electronic systems, 2022-11, Vol.27 (6), p.1-29

2022

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SpecScope: Automating Discovery of Exploitable Spectre Gadgets on Black-Box Microarchitectures

2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024, p.1-6

2024

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IEEE_Xplore

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SAT-Hard Cyclic Logic Obfuscation for Protecting the IP in the Manufacturing Supply Chain

Optimized and Automated Secure IC Design Flow: A Defense-in-Depth Approach

Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits

From Cryptography to Logic Locking: A Survey on the Architecture Evolution of Secure Scan Chains

AVATAR: NN-Assisted Variation Aware Timing Analysis & Reporting for Hardware Trojan Detection

Enabling Micro AI for Securing Edge Devices at Hardware Level

Cognitive and Scalable Technique for Securing IoT Networks Against Malware Epidemics

Advanced Reinforcement Learning Solution for Clock Skew Engineering: Modified Q-Table Update Technique for Peak Current and IR Drop Minimization

Hardware Accelerated Mappers for Hadoop MapReduce Streaming

Analyzing hardware based malware detectors

ICNN: The Iterative Convolutional Neural Network

MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits

Full-Lock: Hard Distributions of SAT instances for Obfuscating Circuits using Fully Configurable Logic and Routing Blocks

A Low Power JPEG2000 Encoder With Iterative and Fault Tolerant Error Concealment

InterLock: an intercorrelated logic and routing locking

NNgSAT: neural network guided SAT attack on logic locked complex structures

ICNN: An iterative implementation of convolutional neural networks to enable energy and computational complexity aware dynamic approximation

Machine Learning-Based Approaches for Energy-Efficiency Prediction and Scheduling in Composite Cores Architectures

Hybrid-shield: accurate and efficient cross-layer countermeasure for run-time detection and mitigation of cache-based side-channel attacks

Ensemble learning for effective run-time hardware-based malware detection: a comprehensive analysis and classification

Energy-efficient acceleration of MapReduce applications using FPGAs

Phased-Guard: Multi-Phase Machine Learning Framework for Detection and Identification of Zero-Day Microarchitectural Side-Channel Attacks

2SMaRT: A Two-Stage Machine Learning-Based Approach for Run-Time Specialized Hardware-Assisted Malware Detection

Breaking the Design and Security Trade-off of Look-up-table–based Obfuscation

SpecScope: Automating Discovery of Exploitable Spectre Gadgets on Black-Box Microarchitectures

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