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Design of Low–power 4-bit Flash ADC Using Multiplexer Based Encoder in 90nm CMOS Process

International Journal of Electronics and Telecommunications, 2022-01, Vol.68 (3), p.565-570

2022

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A New Embedded Clock Gating Technique in 8- bit Synchronous Counter with Reduced Switching Activity for Clock Divider Circuit

WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS, 2023-12, Vol.22, p.195-205

2023

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A 10-bit 200 MS/s pipelined ADC with parallel sampling and switched op-amp sharing technique

Circuit world, 2021-08, Vol.47 (3), p.274-283

2021

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Design and Comparison of Low Power Consumption Binary and Quaternary Multipliers

National Academy science letters, 2024-08, Vol.47 (4), p.379-384

2024

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A Novel low power 2-D to 3-D Array Priority Encoder using Split-Logic Technique for Data Path Applications

WSEAS TRANSACTIONS ON SYSTEMS AND CONTROL, 2022-01, Vol.17, p.42-49

2022

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Differential Voltage Controlled Ring VCO with No Feedback Loop Technique for Radio Frequency Applications

2024 7th International Conference on Devices, Circuits and Systems (ICDCS), 2024, p.200-204

2024

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Analysis of nano sheet field effect transistor based on performance under different temperature and doping concentrations for 12 nm device

Micro and nanostructures (2022), 2024-10, Vol.194, p.207929, Article 207929

2024

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Verification of UART using AHB VIP with Maximum Coverage

2024 7th International Conference on Devices, Circuits and Systems (ICDCS), 2024, p.234-238

2024

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Design of High-Performance Carry Select Adder using Multiplexer based Logic in 90nm Technology

2023 4th International Conference on Signal Processing and Communication (ICSPC), 2023, p.330-333

2023

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Design of Low Power Pass Transistor Logic Based Adders for Multiplier in 90nm CMOS Process

2023 4th International Conference on Signal Processing and Communication (ICSPC), 2023, p.206-210

2023

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A Novel Architecture for 10-bit 40MSPS Low Power Pipelined ADC Using a Simultaneous Capacitor and Op-amp Sharing Technique

SILICON, 2022-06, Vol.14 (9), p.4839-4847

2022

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Design and Analysis of Frequency Synthesizer for Implantable Cardioverter Defibrillator (ICD) in 90 NM Technology

2023 4th International Conference on Signal Processing and Communication (ICSPC), 2023, p.211-215

2023

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A new architecture of Thermometer to Binary code encoder for 4 - bit FLASH ADC in 45nm CMOS process

Przegląd elektrotechniczny, 2023-01, Vol.1 (11), p.190-193

Sam, D.S.Shylu

2023

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Design of Low–power 4-bit Flash ADC Using Multiplexer Based Encoder in 90nm CMOS Process

International Journal of Electronics and Telecommunications, 2022-04, p.565-570

2022

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Performance Analysis of Array Multiplier Using Low-Power 10T Full Adder

Smart Intelligent Computing and Applications, 2018, Vol.104, p.277-285

2018

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Design and Analysis of Two Stage Op-Amp in 180nm CMOS Process

2024 7th International Conference on Devices, Circuits and Systems (ICDCS), 2024, p.253-257

2024

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Design of highly reusable interface for AHB verification module

2022 6th International Conference on Devices, Circuits and Systems (ICDCS), 2022, p.357-359

2022

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Design of Low Power Dynamic Comparator for SAR ADC

2022 6th International Conference on Devices, Circuits and Systems (ICDCS), 2022, p.272-275

2022

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Design of High Speed Time - Interleaved SAR Analog to Digital Converter

2022 6th International Conference on Devices, Circuits and Systems (ICDCS), 2022, p.460-463

2022

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A Novel architecture of a Low Power Folded Cascode OTA in 180nm CMOS process

2021 7th International Conference on Advanced Computing and Communication Systems (ICACCS), 2021, Vol.1, p.95-99

2021

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Effect of metallic substrate and rubber elastic materials over passive constrained layer damping on tool vibration during boring process

Journal of low frequency noise, vibration, and active control, 2024-09, Vol.43 (3), p.1139-1157

2024

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Study on the Influence of Magnetorheological Fluid Damper on Vibration in Rotating Machinery

Romanian Journal of Acoustics and Vibration, 2022-01, Vol.19 (1), p.29-35

2022

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Application of machine learning techniques for churn prediction in the telecom business

Results in engineering, 2024-12, Vol.24, p.103165, Article 103165

2024

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A power efficient delta-sigma ADC with series-bilinear switch capacitor voltage-controlled oscillator

Telkomnika, 2020-10, Vol.18 (5), p.2618-2627

2020

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Study on the Effect of Polyurethane-Based Magnetorheological Foam Damper on Cutting Performance during Hard Turning Process

Smart and sustainable manufacturing systems, 2022-02, Vol.6 (1), p.37-52

2022

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Design of Low–power 4-bit Flash ADC Using Multiplexer Based Encoder in 90nm CMOS Process

A New Embedded Clock Gating Technique in 8- bit Synchronous Counter with Reduced Switching Activity for Clock Divider Circuit

A 10-bit 200 MS/s pipelined ADC with parallel sampling and switched op-amp sharing technique

Design and Comparison of Low Power Consumption Binary and Quaternary Multipliers

A Novel low power 2-D to 3-D Array Priority Encoder using Split-Logic Technique for Data Path Applications

Differential Voltage Controlled Ring VCO with No Feedback Loop Technique for Radio Frequency Applications

Analysis of nano sheet field effect transistor based on performance under different temperature and doping concentrations for 12 nm device

Verification of UART using AHB VIP with Maximum Coverage

Design of High-Performance Carry Select Adder using Multiplexer based Logic in 90nm Technology

Design of Low Power Pass Transistor Logic Based Adders for Multiplier in 90nm CMOS Process

A Novel Architecture for 10-bit 40MSPS Low Power Pipelined ADC Using a Simultaneous Capacitor and Op-amp Sharing Technique

Design and Analysis of Frequency Synthesizer for Implantable Cardioverter Defibrillator (ICD) in 90 NM Technology

A new architecture of Thermometer to Binary code encoder for 4 - bit FLASH ADC in 45nm CMOS process

Design of Low–power 4-bit Flash ADC Using Multiplexer Based Encoder in 90nm CMOS Process

Performance Analysis of Array Multiplier Using Low-Power 10T Full Adder

Design and Analysis of Two Stage Op-Amp in 180nm CMOS Process

Design of highly reusable interface for AHB verification module

Design of Low Power Dynamic Comparator for SAR ADC

Design of High Speed Time - Interleaved SAR Analog to Digital Converter

A Novel architecture of a Low Power Folded Cascode OTA in 180nm CMOS process

Effect of metallic substrate and rubber elastic materials over passive constrained layer damping on tool vibration during boring process

Study on the Influence of Magnetorheological Fluid Damper on Vibration in Rotating Machinery

Application of machine learning techniques for churn prediction in the telecom business

A power efficient delta-sigma ADC with series-bilinear switch capacitor voltage-controlled oscillator

Study on the Effect of Polyurethane-Based Magnetorheological Foam Damper on Cutting Performance during Hard Turning Process

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