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A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity Tolerance

IEEE journal of solid-state circuits, 2020-02, Vol.55 (2), p.344-355

2020

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A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration

IEEE journal of solid-state circuits, 2020-03, Vol.55 (3), p.693-705

2020

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A Fully Integrated Digital LDO With Coarse-Fine-Tuning and Burst-Mode Operation

IEEE transactions on circuits and systems. II, Express briefs, 2016-07, Vol.63 (7), p.683-687

2016

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A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time-Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward

IEEE journal of solid-state circuits, 2023-10, Vol.58 (10), p.1-11

2023

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A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS

IEEE journal of solid-state circuits, 2010-06, Vol.45 (6), p.1111-1121

2010

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A 10MHz-BW 85dB-DR CT 0-4 MASH Delta-Sigma Modulator Achieving + 5dBFS MSA

IEEE transactions on circuits and systems. I, Regular papers, 2023-12, Vol.70 (12), p.1-12

2023

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A Two-Channel Time-Interleaved Continuous-Time Third-Order CIFF-Based Delta-Sigma Modulator

IEEE transactions on circuits and systems. I, Regular papers, 2023-12, Vol.70 (12), p.1-13

2023

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A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing

IEEE transactions on circuits and systems. I, Regular papers, 2023-12, Vol.70 (12), p.1-14

2023

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A 95% Peak Efficiency Modified KY Converter With Improved Flying Capacitor Charging in DCM for IoT Applications

IEEE journal of solid-state circuits, 2023-11, Vol.58 (11), p.1-12

2023

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A Wide Input Range Dual-Path CMOS Rectifier for RF Energy Harvesting

IEEE transactions on circuits and systems. II, Express briefs, 2017-02, Vol.64 (2), p.166-170

2017

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High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based Calibration for Nonlinear Amplitude and Phase Distortion

IEEE transactions on circuits and systems. I, Regular papers, 2022-12, Vol.69 (12), p.4944-4957

2022

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A 470-nA Quiescent Current and 92.7%/94.7% Efficiency DCT/PWM Control Buck Converter With Seamless Mode Selection for IoT Application

IEEE transactions on circuits and systems. I, Regular papers, 2020-11, Vol.67 (11), p.4085-4098

2020

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A Two-phase Multi-bit Incremental ADC with Variable Loop Order

IEEE transactions on circuits and systems. II, Express briefs, 2023-08, Vol.70 (8), p.1-1

2023

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On the Synthesis of Continuous-Time Sturdy MASH Delta-Sigma Modulators

IEEE transactions on circuits and systems. II, Express briefs, 2023-02, Vol.70 (2), p.356-360

2023

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A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current

IEEE transactions on circuits and systems. II, Express briefs, 2018-10, Vol.65 (10), p.1380-1384

2018

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LDO-Free Power Management System: A 10-bit Pipelined ADC Directly Powered by Inductor-Based Boost Converter With Ripple Calibration

IEEE transactions on circuits and systems. I, Regular papers, 2020-12, Vol.67 (12), p.4174-4186

2020

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A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH \Delta \Sigma Modulator With Multirate Opamp Sharing

IEEE transactions on circuits and systems. I, Regular papers, 2017-10, Vol.64 (10), p.2641-2654

2017

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A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC

IEEE journal of solid-state circuits, 2016-02, Vol.51 (2), p.365-377

2016

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Bird's‐eye view of analog and mixed‐signal chips for the 21st century

International journal of circuit theory and applications, 2021-03, Vol.49 (3), p.746-761

2021

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A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC

IEEE transactions on circuits and systems. I, Regular papers, 2017-08, Vol.64 (8), p.1966-1976

2017

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Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators

IEEE transactions on circuits and systems. II, Express briefs, 2016-09, Vol.63 (9), p.903-907

2016

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Accuracy-Enhanced Variance-Based Time-Skew Calibration Using SAR as Window Detector

IEEE transactions on very large scale integration (VLSI) systems, 2019-02, Vol.27 (2), p.481-485

2019

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A 160MHz-BW 68dB-SNDR 30.8mW Continuous-Time Pipeline DSM with Correlative Passive Low-Pass Filters and DAC Image Pre-Filtering

2024 IEEE Custom Integrated Circuits Conference (CICC), 2024, p.1-2

2024

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A 15MHz-BW 82.7dB-SNDR 98.8dB-SFDR Pipelined MASH 2-2 CT DSM in 65nm CMOS

2024 IEEE Custom Integrated Circuits Conference (CICC), 2024, p.1-2

2024

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An Integrated DC-DC Converter With Segmented Frequency Modulation and Multiphase Co-Work Control for Fast Transient Recovery

IEEE journal of solid-state circuits, 2019-10, Vol.54 (10), p.2637-2648

2019

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A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity Tolerance

A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration

A Fully Integrated Digital LDO With Coarse-Fine-Tuning and Burst-Mode Operation

A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time-Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward

A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS

A 10MHz-BW 85dB-DR CT 0-4 MASH Delta-Sigma Modulator Achieving + 5dBFS MSA

A Two-Channel Time-Interleaved Continuous-Time Third-Order CIFF-Based Delta-Sigma Modulator

A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing

A 95% Peak Efficiency Modified KY Converter With Improved Flying Capacitor Charging in DCM for IoT Applications

A Wide Input Range Dual-Path CMOS Rectifier for RF Energy Harvesting

High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based Calibration for Nonlinear Amplitude and Phase Distortion

A 470-nA Quiescent Current and 92.7%/94.7% Efficiency DCT/PWM Control Buck Converter With Seamless Mode Selection for IoT Application

A Two-phase Multi-bit Incremental ADC with Variable Loop Order

On the Synthesis of Continuous-Time Sturdy MASH Delta-Sigma Modulators

A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current

LDO-Free Power Management System: A 10-bit Pipelined ADC Directly Powered by Inductor-Based Boost Converter With Ripple Calibration

A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH \Delta \Sigma Modulator With Multirate Opamp Sharing

A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC

Bird's‐eye view of analog and mixed‐signal chips for the 21st century

A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC

Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators

Accuracy-Enhanced Variance-Based Time-Skew Calibration Using SAR as Window Detector

A 160MHz-BW 68dB-SNDR 30.8mW Continuous-Time Pipeline DSM with Correlative Passive Low-Pass Filters and DAC Image Pre-Filtering

A 15MHz-BW 82.7dB-SNDR 98.8dB-SFDR Pipelined MASH 2-2 CT DSM in 65nm CMOS

An Integrated DC-DC Converter With Segmented Frequency Modulation and Multiphase Co-Work Control for Fast Transient Recovery

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