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A modular approach to build a hardware testbed for cloud resource management research

The Journal of supercomputing, 2024-05, Vol.80 (8), p.10552-10583

2024

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Cache-Hierarchy Contention-Aware Scheduling in CMPs

IEEE transactions on parallel and distributed systems, 2014-03, Vol.25 (3), p.581-590

2014

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Segment Switching: A New Switching Strategy for Optical HPC Networks

IEEE access, 2021, Vol.9, p.43095-43106

2021

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Main memory controller with multiple media technologies for big data workloads

Journal of big data, 2023-12, Vol.10 (1), p.75-19, Article 75

2023

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Phase-Aware Cache Partitioning to Target Both Turnaround Time and System Performance

IEEE transactions on parallel and distributed systems, 2020-11, Vol.31 (11), p.2556-2568

2020

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Thread Isolation to Improve Symbiotic Scheduling on SMT Multicore Processors

IEEE transactions on parallel and distributed systems, 2020-02, Vol.31 (2), p.359-373

2020

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VMT: Virtualized Multi-Threading for Accelerating Graph Workloads on Commodity Processors

IEEE transactions on computers, 2022-06, Vol.71 (6), p.1386-1398

2022

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Accurately modeling the on-chip and off-chip GPU memory subsystem

Future generation computer systems, 2018-05, Vol.82, p.510-519

2018

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Hy-Sched: A Simple Hyperthreading-Aware Thread to Core Allocation Strategy

IEEE computer architecture letters, 2021-01, Vol.20 (1), p.26-29

2021

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Efficient Management of Cache Accesses to Boost GPGPU Memory Subsystem Performance

IEEE transactions on computers, 2019-10, Vol.68 (10), p.1442-1454

2019

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DeepP: Deep Learning Multi-Program Prefetch Configuration for the IBM POWER 8

IEEE transactions on computers, 2022-10, Vol.71 (10), p.2646-2658

2022

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Bandwidth-Aware Dynamic Prefetch Configuration for IBM POWER8

IEEE transactions on parallel and distributed systems, 2020-08, Vol.31 (8), p.1970-1982

2020

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Perf&Fair: A Progress-Aware Scheduler to Enhance Performance and Fairness in SMT Multicores

IEEE transactions on computers, 2017-05, Vol.66 (5), p.905-911

2017

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Cloud White: Detecting and Estimating QoS Degradation of Latency-Critical Workloads in the Public Cloud

Future generation computer systems, 2023-01, Vol.138, p.13-25

2023

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Bandwidth-Aware On-Line Scheduling in SMT Multicores

IEEE transactions on computers, 2016-02, Vol.65 (2), p.422-434

2016

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Cache-Poll: Containing Pollution in Non-Inclusive Caches Through Cache Partitioning

Proceedings of the 51st International Conference on Parallel Processing, 2022, p.1-11

2022

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Effect of Hyper-Threading in Latency-Critical Multithreaded Cloud Applications and Utilization Analysis of the Major System Resources

Future generation computer systems, 2022-06, Vol.131, p.194-208

2022

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Foreword to the Special Issue on Processors, Interconnects, Storage, and Caches for Exascale Systems

Concurrency and computation, 2019-11, Vol.31 (21), p.n/a

2019

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An Aging-Aware GPU Register File Design Based on Data Redundancy

IEEE transactions on computers, 2019-01, Vol.68 (1), p.4-20

2019

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An efficient cache flat storage organization for multithreaded workloads for low power processors

Future generation computer systems, 2020-09, Vol.110, p.1037-1054

2020

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Designing lab sessions focusing on real processors for computer architecture courses: A practical perspective

Journal of parallel and distributed computing, 2018-08, Vol.118, p.128-139

2018

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Dynamic Allocation of Processor Cores to Graph Applications on Commodity Servers

2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT), 2023, p.323-324

2023

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Way Combination for an Adaptive and Scalable Coherence Directory

IEEE transactions on parallel and distributed systems, 2019-11, Vol.30 (11), p.2608-2623

2019

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A Hardware Approach to Fairly Balance the Inter-Thread Interference in Shared Caches

IEEE transactions on parallel and distributed systems, 2017-11, Vol.28 (11), p.3021-3032

2017

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On Microarchitectural Mechanisms for Cache Wearout Reduction

IEEE transactions on very large scale integration (VLSI) systems, 2017-03, Vol.25 (3), p.857-871

2017

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A modular approach to build a hardware testbed for cloud resource management research

Cache-Hierarchy Contention-Aware Scheduling in CMPs

Segment Switching: A New Switching Strategy for Optical HPC Networks

Main memory controller with multiple media technologies for big data workloads

Phase-Aware Cache Partitioning to Target Both Turnaround Time and System Performance

Thread Isolation to Improve Symbiotic Scheduling on SMT Multicore Processors

VMT: Virtualized Multi-Threading for Accelerating Graph Workloads on Commodity Processors

Accurately modeling the on-chip and off-chip GPU memory subsystem

Hy-Sched: A Simple Hyperthreading-Aware Thread to Core Allocation Strategy

Efficient Management of Cache Accesses to Boost GPGPU Memory Subsystem Performance

DeepP: Deep Learning Multi-Program Prefetch Configuration for the IBM POWER 8

Bandwidth-Aware Dynamic Prefetch Configuration for IBM POWER8

Perf&Fair: A Progress-Aware Scheduler to Enhance Performance and Fairness in SMT Multicores

Cloud White: Detecting and Estimating QoS Degradation of Latency-Critical Workloads in the Public Cloud

Bandwidth-Aware On-Line Scheduling in SMT Multicores

Cache-Poll: Containing Pollution in Non-Inclusive Caches Through Cache Partitioning

Effect of Hyper-Threading in Latency-Critical Multithreaded Cloud Applications and Utilization Analysis of the Major System Resources

Foreword to the Special Issue on Processors, Interconnects, Storage, and Caches for Exascale Systems

An Aging-Aware GPU Register File Design Based on Data Redundancy

An efficient cache flat storage organization for multithreaded workloads for low power processors

Designing lab sessions focusing on real processors for computer architecture courses: A practical perspective

Dynamic Allocation of Processor Cores to Graph Applications on Commodity Servers

Way Combination for an Adaptive and Scalable Coherence Directory

A Hardware Approach to Fairly Balance the Inter-Thread Interference in Shared Caches

On Microarchitectural Mechanisms for Cache Wearout Reduction

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