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Attacking Deep Learning AI Hardware with Universal Adversarial Perturbation

Information (Basel), 2023-09, Vol.14 (9), p.516

2023

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Test and Yield Loss Reduction of AI and Deep Learning Accelerators

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-01, Vol.41 (1), p.104-115

2022

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System and Design Technology Co-Optimization of SOT-MRAM for High-Performance AI Accelerator Memory System

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-04, Vol.43 (4), p.1065-1078

2024

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Designing Efficient and High-Performance AI Accelerators With Customized STT-MRAM

IEEE transactions on very large scale integration (VLSI) systems, 2021-10, Vol.29 (10), p.1730-1742

2021

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Design of a Network of Digital Sensor Macros for Extracting Power Supply Noise Profile in SoCs

IEEE transactions on very large scale integration (VLSI) systems, 2016-05, Vol.24 (5), p.1702-1714

2016

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Effects of Temperature and Structural Geometries on a Skyrmion Logic Gate

IEEE transactions on electron devices, 2022-04, Vol.69 (4), p.1706-1712

2022

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Special Session: Reliability Analysis for AI/ML Hardware

2021 IEEE 39th VLSI Test Symposium (VTS), 2021, p.1-10

2021

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Special Session: On the Reliability of Conventional and Quantum Neural Network Hardware

2022 IEEE 40th VLSI Test Symposium (VTS), 2022, p.1-12

2022

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SoC Speed Binning Using Machine Learning and On-Chip Slack Sensors

IEEE transactions on computer-aided design of integrated circuits and systems, 2017-05, Vol.36 (5), p.842-854

2017

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Design of Reliable SoCs With BIST Hardware and Machine Learning

IEEE transactions on very large scale integration (VLSI) systems, 2017-11, Vol.25 (11), p.3237-3250

2017

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Hardware trojan detection through information flow security verification

2017 IEEE International Test Conference (ITC), 2017, p.1-10

2017

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Soft-HaT: Software-Based Silicon Reprogramming for Hardware Trojan Implementation

ACM transactions on design automation of electronic systems, 2020-09, Vol.25 (4), p.1-22

2020

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On-Chip Structures for Reliability Management of System-on-Chips

Sadi, Mehdi

2017

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Power delivery in 3D packages: Current crowding effects, dynamic IR drop and compensation network using sensors

2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2016, p.1-6

2016

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TRO: An On-Chip Ring Oscillator-Based GHz Transient IR-Drop Monitor

IEEE transactions on computer-aided design of integrated circuits and systems, 2017-05, Vol.36 (5), p.855-868

2017

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System and Design Technology Co-optimization of Chiplet-based AI Accelerator with Machine Learning

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023, p.697-702

2023

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BIST-RM: BIST-assisted reliability management of SoCs using on-chip clock sweeping and machine learning

2016 IEEE International Test Conference (ITC), 2016, p.1-10

2016

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Homomorphic Encryption

Emerging Topics in Hardware Security, 2021, p.281-307

2021

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An All Digital Distributed Sensor Network Based Framework for Continuous Noise Monitoring and Timing Failure Analysis in SoCs

2014 IEEE 23rd Asian Test Symposium, 2014, p.269-274

2014

Volltextzugriff (PDF)

True Random Number Generation using Latency Variations of Commercial MRAM Chips

2021 22nd International Symposium on Quality Electronic Design (ISQED), 2021, p.510-515

2021

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Design of a digital IP for 3D-IC die-to-die clock synchronization

2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, p.1-4

2017

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Speed Binning Using Machine Learning And On-chip Slack Sensors

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 2015, p.155-160

2015

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Design of near threshold All Digital Delay Locked Loops

2012 IEEE International SOC Conference, 2012, p.137-142

2012

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An efficient all-digital IR-Drop Alarmer for DVFS-based SoC

2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016, p.221-224

2016

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Temperature sensitivity forecasting of electrical load

2010 4th International Power Engineering and Optimization Conference (PEOCO), 2010, p.244-248

2010

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Attacking Deep Learning AI Hardware with Universal Adversarial Perturbation

Test and Yield Loss Reduction of AI and Deep Learning Accelerators

System and Design Technology Co-Optimization of SOT-MRAM for High-Performance AI Accelerator Memory System

Designing Efficient and High-Performance AI Accelerators With Customized STT-MRAM

Design of a Network of Digital Sensor Macros for Extracting Power Supply Noise Profile in SoCs

Effects of Temperature and Structural Geometries on a Skyrmion Logic Gate

Special Session: Reliability Analysis for AI/ML Hardware

Special Session: On the Reliability of Conventional and Quantum Neural Network Hardware

SoC Speed Binning Using Machine Learning and On-Chip Slack Sensors

Design of Reliable SoCs With BIST Hardware and Machine Learning

Hardware trojan detection through information flow security verification

Soft-HaT: Software-Based Silicon Reprogramming for Hardware Trojan Implementation

On-Chip Structures for Reliability Management of System-on-Chips

Power delivery in 3D packages: Current crowding effects, dynamic IR drop and compensation network using sensors

TRO: An On-Chip Ring Oscillator-Based GHz Transient IR-Drop Monitor

System and Design Technology Co-optimization of Chiplet-based AI Accelerator with Machine Learning

BIST-RM: BIST-assisted reliability management of SoCs using on-chip clock sweeping and machine learning

Homomorphic Encryption

An All Digital Distributed Sensor Network Based Framework for Continuous Noise Monitoring and Timing Failure Analysis in SoCs

True Random Number Generation using Latency Variations of Commercial MRAM Chips

Design of a digital IP for 3D-IC die-to-die clock synchronization

Speed Binning Using Machine Learning And On-chip Slack Sensors

Design of near threshold All Digital Delay Locked Loops

An efficient all-digital IR-Drop Alarmer for DVFS-based SoC

Temperature sensitivity forecasting of electrical load

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