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Effects of floating-gate interference on NAND flash memory cell operation

IEEE electron device letters, 2002-05, Vol.23 (5), p.264-266

2002

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Charge-trapping device structure of SiO2∕SiN∕high-k dielectric Al2O3 for high-density flash memory

Applied physics letters, 2005-04, Vol.86 (15)

2005

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13.3 A 280-Layer 1Tb 4b/cell 3D-NAND Flash Memory with a 28.5Gb/mm2 Areal Density and a 3.2GB/s High-Speed IO Rate

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.236-237

2024

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A physical-based analytical turn-on model of polysilicon thin-film transistors for circuit simulation

IEEE transactions on electron devices, 1999-01, Vol.46 (1), p.165-172

1999

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The Effect of Trapped Charge Distributions on Data Retention Characteristics of nand Flash Memory Cells

IEEE electron device letters, 2007-08, Vol.28 (8), p.750-752

2007

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The Effect of Field Oxide Recess on Cell VTH Distribution of NAND Flash Cell Arrays

IEEE electron device letters, 2008, Vol.29 (9), p.1050-1052

2008

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The Effect of Field Oxide Recess on Cell V Distribution of nand Flash Cell Arrays

IEEE electron device letters, 2008-09, Vol.29 (9), p.1050-1052

2008

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Highly reliable polysilicon oxide grown by electron cyclotron resonance nitrous oxide plasma

IEEE electron device letters, 1997-10, Vol.18 (10), p.486-488

1997

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Oxidation of Silicon Using Electron Cyclotron Resonance Nitrous Oxide Plasma and Its Application to Polycrystalline Silicon Thin Film Transistors

Journal of the Electrochemical Society, 1997-09, Vol.144 (9), p.3283-3287

1997

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A poly-Si thin-film transistor EEPROM cell with a folded floating gate

IEEE transactions on electron devices, 1999-02, Vol.46 (2), p.436-438

1999

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Innovative Barrier Metal-Less Metal Gate Scheme Leading to Highly Reliable Cell Characteristics for 8th Generation 512Gb 3D NAND Flash Memory

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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Nonvolatile SRAM cell using different capacitance loading

Electronics letters, 1998-02, Vol.34 (3), p.251

1998

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Novel Strategies for Highly Uniform and Reliable Cell Characteristics of 8th Generation 1Tb 3D-NAND Flash Memory

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023, p.1-2

2023

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Suppression of leakage current in n-channel polysilicon thin-film transistors using NH3 annealing

Japanese journal of applied physics, 1995, Vol.34 (2B), p.882-885

1995

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The Effect of Field Oxide Recess on Cell [Formula Omitted] Distribution of nand Flash Cell Arrays

IEEE electron device letters, 2008-09, Vol.29 (9), p.1050

2008

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The Effect of Field Oxide Recess on Cell [V_{rm TH}] Distribution of @@inand@ Flash Cell Arrays

IEEE electron device letters, 2008-09, Vol.29 (9), p.1050-1052

2008

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The Effect of Field Oxide Recess on Cell V rm TH Distribution of nand Flash Cell Arrays

IEEE electron device letters, 2008-01, Vol.29 (9)

2008

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Suppression of Leakage Current in n-Channel Polysilicon Thin-Film Transistors Using NH 3 Annealing

Japanese Journal of Applied Physics, 1995-02, Vol.34 (2S), p.882

1995

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Effects of ECR N2O-Plasma Nitridation on Thermal Oxide Characteristics

MRS proceedings, 1995, Vol.391

1995

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A Model for the Frequency Dependence of Charge Pumping Current in Polycrystalline Silicon Thin Film Transistor

MRS proceedings, 1995, Vol.378, p.761-766, Article 761

1995

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Charge-trapping device structure of Si O 2 ∕ Si N ∕ high - k dielectric Al 2 O 3 for high-density flash memory

Applied physics letters, 2005-04, Vol.86 (15), p.152908-152908-3

2005

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A new floating gate cell structure with a silicon-nitride cap layer for sub-20 nm NAND flash memory

2010 Symposium on VLSI Technology, 2010, p.127-128

2010

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A highly manufacturable low-k ALD-SiBN process for 60nm NAND flash devices and beyond

IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004, 2004, p.1063-1066

2004

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Effect of low-k dielectric material on 63nm MLC (multi-level cell) NAND flash cell arrays

IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech), 2005, p.37-38

2005

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A physical-based analytical turn-on model of polysilicon thin film transistors for circuit simulation

Proceedings of International Electron Devices Meeting, 1995, p.953-956

1995

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Effects of floating-gate interference on NAND flash memory cell operation

Charge-trapping device structure of SiO2∕SiN∕high-k dielectric Al2O3 for high-density flash memory

13.3 A 280-Layer 1Tb 4b/cell 3D-NAND Flash Memory with a 28.5Gb/mm2 Areal Density and a 3.2GB/s High-Speed IO Rate

A physical-based analytical turn-on model of polysilicon thin-film transistors for circuit simulation

The Effect of Trapped Charge Distributions on Data Retention Characteristics of nand Flash Memory Cells

The Effect of Field Oxide Recess on Cell VTH Distribution of NAND Flash Cell Arrays

The Effect of Field Oxide Recess on Cell V Distribution of nand Flash Cell Arrays

Highly reliable polysilicon oxide grown by electron cyclotron resonance nitrous oxide plasma

Oxidation of Silicon Using Electron Cyclotron Resonance Nitrous Oxide Plasma and Its Application to Polycrystalline Silicon Thin Film Transistors

A poly-Si thin-film transistor EEPROM cell with a folded floating gate

Innovative Barrier Metal-Less Metal Gate Scheme Leading to Highly Reliable Cell Characteristics for 8th Generation 512Gb 3D NAND Flash Memory

Nonvolatile SRAM cell using different capacitance loading

Novel Strategies for Highly Uniform and Reliable Cell Characteristics of 8th Generation 1Tb 3D-NAND Flash Memory

Suppression of leakage current in n-channel polysilicon thin-film transistors using NH3 annealing

The Effect of Field Oxide Recess on Cell [Formula Omitted] Distribution of nand Flash Cell Arrays

The Effect of Field Oxide Recess on Cell [V_{rm TH}] Distribution of @@inand@ Flash Cell Arrays

The Effect of Field Oxide Recess on Cell V rm TH Distribution of nand Flash Cell Arrays

Suppression of Leakage Current in n-Channel Polysilicon Thin-Film Transistors Using NH 3 Annealing

Effects of ECR N2O-Plasma Nitridation on Thermal Oxide Characteristics

A Model for the Frequency Dependence of Charge Pumping Current in Polycrystalline Silicon Thin Film Transistor

Charge-trapping device structure of Si O 2 ∕ Si N ∕ high - k dielectric Al 2 O 3 for high-density flash memory

A new floating gate cell structure with a silicon-nitride cap layer for sub-20 nm NAND flash memory

A highly manufacturable low-k ALD-SiBN process for 60nm NAND flash devices and beyond

Effect of low-k dielectric material on 63nm MLC (multi-level cell) NAND flash cell arrays

A physical-based analytical turn-on model of polysilicon thin film transistors for circuit simulation

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