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Dynamic Vpass Controlled Program Scheme and Optimized Erase Vth Control for High Program Inhibition in MLC NAND Flash Memories

IEEE journal of solid-state circuits, 2010-10, Vol.45 (10), p.2165-2172

2010

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A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme

IEEE journal of solid-state circuits, 1995-11, Vol.30 (11), p.1149-1156

1995

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New scaling limitation of the floating gate cell in NAND Flash Memory

2010 IEEE International Reliability Physics Symposium, 2010, p.599-603

2010

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A dual-mode NAND flash memory: 1-Gb multilevel and high-performance 512-Mb single-level modes

IEEE journal of solid-state circuits, 2001-11, Vol.36 (11), p.1700-1706

2001

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A 90-nm CMOS 1.8-V 2-Gb NAND flash memory for mass storage applications

IEEE journal of solid-state circuits, 2003-11, Vol.38 (11), p.1934-1942

2003

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32nm 3-bit 32Gb NAND Flash Memory with DPT (d̲ouble p̲atterning t̲echnology) process for mass production

2010 Symposium on VLSI Technology, 2010, p.125-126

2010

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Improving Read Disturb Characteristics by Using Double Common Source Line and Dummy Switch Architecture in Multi Level Cell NAND Flash Memory with Low Power Consumption

Japanese Journal of Applied Physics, 2011-04, Vol.50 (4), p.04DD03-04DD03-4

2011

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A 3.3-V, 4-Mb nonvolatile ferroelectric RAM with selectively driven double-pulsed plate read/write-back scheme

IEEE journal of solid-state circuits, 2000-05, Vol.35 (5), p.697-704

2000

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Optimal cell design for enhancing reliability characteristics for sub 30 nm NAND Flash memory

2010 IEEE International Reliability Physics Symposium, 2010, p.611-614

2010

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Impact of floating gate dry etching on erase characteristics in NOR flash memory

IEEE electron device letters, 2002-08, Vol.23 (8), p.476-478

2002

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High-performance 1-Gb-NAND flash memory with 0.12-μm technology

IEEE journal of solid-state circuits, 2002-11, Vol.37 (11), p.1502-1509

2002

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A 3.3-V single power supply 16-Mb nonvolatile virtual DRAM using a NAND flash memory technology

IEEE journal of solid-state circuits, 1997-11, Vol.32 (11), p.1748-1757

1997

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0.4- mu m 3.3-V 1T1C 4-Mb nonvolatile ferroelectric RAM with fixed bitline reference voltage scheme and data protection circuit

IEEE journal of solid-state circuits, 2000-11, Vol.35 (11), p.1690-1694

2000

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Influence of plasma edge damage on erase characteristics of NOR flash EEPROM using channel erase method

2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320), 2002, p.354-358

2002

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3.3V 128Mb multi-level NAND flash memory for mass storage applications

Digest of technical papers - IEEE International Solid-State Circuits Conference, 1996, Vol.39, p.32-33

1996

Volltextzugriff (PDF)

NAND Flash Memory Technology

Nonvolatile Memory Technologies with Emphasis on Flash, 2007, Vol.8, p.223-311

1, 2007

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8-bit-resolution, 360- mu s write time nonvolatile analog memory based on Differentially Balanced Constant-Tunneling-Current Scheme (DBCS)

IEEE journal of solid-state circuits, 1998-11, Vol.33 (11), p.1758-1762

1998

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An analysis for the potential of floating guard rings

Solid-state electronics, 1990-09, Vol.33 (9), p.1125-1129

1990

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A 1.8 V 1 Gb NAND flash memory with 0.12 mu m STI process technology

Digest of technical papers - IEEE International Solid-State Circuits Conference, 2002-01, p.80-81+410

2002

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A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme

Proceedings ISSCC '95 - International Solid-State Circuits Conference, 1995, p.128-129

1995

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A self-consistent analytic threshold voltage model for thin SOI n-channel MOSFETs

Solid-state electronics, 1991-12, Vol.34 (12), p.1421-1425

1991

Volltextzugriff (PDF)

A Comparison between 63nm 8Gb and 90nm 4Gb Multi-Level Cell NAND Flash Memory for Mass Storage Application

2005 IEEE Asian Solid-State Circuits Conference, 2005, p.13-16

2005

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A highly manufacturable integration technology for 27nm 2 and 3bit/cell NAND flash memory

2010 International Electron Devices Meeting, 2010, p.5.1.1-5.1.4

2010

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Data retention failure in NOR flash memory cells

2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167), 2001, p.57-60

2001

Volltextzugriff (PDF)

Improving Read Disturb Characteristics by Using Double Common Source Line and Dummy Switch Architecture in Multi Level Cell NAND Flash Memory with Low Power Consumption

Japanese Journal of Applied Physics, 2011-04, Vol.50 (4S), p.4

2011

Volltextzugriff (PDF)

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Dynamic Vpass Controlled Program Scheme and Optimized Erase Vth Control for High Program Inhibition in MLC NAND Flash Memories

A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme

New scaling limitation of the floating gate cell in NAND Flash Memory

A dual-mode NAND flash memory: 1-Gb multilevel and high-performance 512-Mb single-level modes

A 90-nm CMOS 1.8-V 2-Gb NAND flash memory for mass storage applications

32nm 3-bit 32Gb NAND Flash Memory with DPT (d̲ouble p̲atterning t̲echnology) process for mass production

Improving Read Disturb Characteristics by Using Double Common Source Line and Dummy Switch Architecture in Multi Level Cell NAND Flash Memory with Low Power Consumption

A 3.3-V, 4-Mb nonvolatile ferroelectric RAM with selectively driven double-pulsed plate read/write-back scheme

Optimal cell design for enhancing reliability characteristics for sub 30 nm NAND Flash memory

Impact of floating gate dry etching on erase characteristics in NOR flash memory

High-performance 1-Gb-NAND flash memory with 0.12-μm technology

A 3.3-V single power supply 16-Mb nonvolatile virtual DRAM using a NAND flash memory technology

0.4- mu m 3.3-V 1T1C 4-Mb nonvolatile ferroelectric RAM with fixed bitline reference voltage scheme and data protection circuit

Influence of plasma edge damage on erase characteristics of NOR flash EEPROM using channel erase method

3.3V 128Mb multi-level NAND flash memory for mass storage applications

NAND Flash Memory Technology

8-bit-resolution, 360- mu s write time nonvolatile analog memory based on Differentially Balanced Constant-Tunneling-Current Scheme (DBCS)

An analysis for the potential of floating guard rings

A 1.8 V 1 Gb NAND flash memory with 0.12 mu m STI process technology

A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme

A self-consistent analytic threshold voltage model for thin SOI n-channel MOSFETs

A Comparison between 63nm 8Gb and 90nm 4Gb Multi-Level Cell NAND Flash Memory for Mass Storage Application

A highly manufacturable integration technology for 27nm 2 and 3bit/cell NAND flash memory

Data retention failure in NOR flash memory cells

Improving Read Disturb Characteristics by Using Double Common Source Line and Dummy Switch Architecture in Multi Level Cell NAND Flash Memory with Low Power Consumption

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