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Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip

IEICE Transactions on Information and Systems, 2014, Vol.E97.D(9), pp.2304-2311

2014

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High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs

IEICE Transactions on Information and Systems, 2014/06/01, Vol.E97.D(6), pp.1546-1556

2014

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Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using a Completion-Detection Scheme

IEICE Transactions on Information and Systems, 2010/08/01, Vol.E93.D(8), pp.2080-2088

2010

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Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic

IEICE transactions on electronics, 2006-11, Vol.E89-C (11), p.1591-1597

2006

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Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System

2009 39th International Symposium on Multiple-Valued Logic, 2009, p.60-65

2009

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Design of a Quaternary Single-Ended Current-Mode Circuit for an Energy-Efficient Inter-chip Asynchronous Communication Link

2014 IEEE 44th International Symposium on Multiple-Valued Logic, 2014, p.67-72

2014

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Energy-aware current-mode inter-chip link for a dependable GALS NoC platform

2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014, p.1865-1868

2014

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Design of High-Performance Quaternary Adders Based on Output-Generator Sharing

38th International Symposium on Multiple Valued Logic (ismvl 2008), 2008, p.8-13

2008

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Design and Evaluation of a 54 x 54-bit Multiplier Based on Differential-Pair Circuitry

IEICE transactions on electronics, 2007-04, Vol.E90-C (4), p.683-691

2007

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Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor

37th International Symposium on Multiple-Valued Logic (ISMVL'07), 2007, p.43-43

2007

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Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits

36th International Symposium on Multiple-Valued Logic (ISMVL'06), 2006, p.14-14

2006

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Highly reliable single-ended current-mode circuit for an inter-chip asynchronous communication link

2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2014, p.683-686

2014

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Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip

High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs

Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using a Completion-Detection Scheme

Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic

Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System

Design of a Quaternary Single-Ended Current-Mode Circuit for an Energy-Efficient Inter-chip Asynchronous Communication Link

Energy-aware current-mode inter-chip link for a dependable GALS NoC platform

Design of High-Performance Quaternary Adders Based on Output-Generator Sharing

Design and Evaluation of a 54 x 54-bit Multiplier Based on Differential-Pair Circuitry

Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor

Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits

Highly reliable single-ended current-mode circuit for an inter-chip asynchronous communication link

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