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A Dual-Mode In-Memory Computing Unit Using Spin Hall-Assisted MRAM for Data-Intensive Applications

IEEE transactions on magnetics, 2021-04, Vol.57 (4), p.1-10

2021

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Energy Efficient Ternary Multi-trit Multiplier Design Using Novel Adders

Circuits, systems, and signal processing, 2024-07, Vol.43 (7), p.4050-4072

2024

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Design of a STT-MTJ Based Random-Access Memory With In-situ Processing for Data-Intensive Applications

IEEE transactions on nanotechnology, 2022, Vol.21, p.455-465

2022

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An optimal delay aware task assignment scheme for wireless SDN networked edge cloudlets

Future generation computer systems, 2020-01, Vol.102, p.862-875

2020

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Design of a novel CMOS/MTJ-based multibit SRAM cell with low store energy for IoT applications

International journal of electronics, 2020-06, Vol.107 (6), p.899-914

2020

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Energy-efficient data retention in D flip-flops using STT-MTJ

Circuit world, 2020-10, Vol.46 (4), p.229-241

2020

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Design of a tunable delay line with on-chip calibration to generate process-invariant PWM signal for in-memory computing

Analog integrated circuits and signal processing, 2023-08, Vol.116 (1-2), p.5-13

2023

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E-SATS: An Efficient and Simple Time Synchronization Protocol for Cluster- Based Wireless Sensor Networks

IEEE sensors journal, 2019-11, Vol.19 (21), p.10144-10156

2019

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Design of a Low Power Approximate Adder based on Magnetic Tunnel Junction for Image Processing Applications

2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2021, p.1-2

2021

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Design of an MTJ/CMOS-Based Asynchronous System for Ultra-Low Power Energy Autonomous Applications

Journal of circuits, systems, and computers, 2021-03, Vol.30 (4), p.2150058

2021

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A low power high speed MTJ based non-volatile SRAM cell for energy harvesting based IoT applications

Integration (Amsterdam), 2019-03, Vol.65, p.43-50

2019

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Integrated Cooperative Synchronization for Wireless Sensor Networks

IEEE wireless communications letters, 2019-06, Vol.8 (3), p.701-704

2019

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An efficient adaptive block pinning for multicore architectures

Microprocessors and microsystems, 2015-05, Vol.39 (3), p.181-188

2015

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An exploration of neuromorphic systems and related design issues/challenges in dark silicon era

IOP conference series. Materials Science and Engineering, 2018-03, Vol.331 (1), p.12003

2018

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A testbed validated simple time synchronization protocol for clustered wireless sensor networks for IoT

Journal of intelligent & fuzzy systems, 2019-01, Vol.36 (5), p.4531-4543

2019

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A Novel Architecture for FPGA Implementation of Otsu's Global Automatic Image Thresholding Algorithm

2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014, p.300-305

2014

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Study of Various Factors Affecting Performance of Multi-Core Processors

International journal of distributed and parallel systems, 2013-07, Vol.4 (4), p.37-45

2013

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Register Allocation For Fine Grain Threads On Multicore Processor

Journal of King Saud University. Computer and information sciences, 2017, Vol.29 (1), p.85-92

2017

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Global Scheduling Heuristics for Multicore Architecture

Scientific programming, 2015-01, Vol.2015 (2015), p.1-12

2015

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Design of In-Memory Computing Enabled SRAM Macro

2022 IEEE 19th India Council International Conference (INDICON), 2022, p.1-4

2022

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Compiler Driven Inter Block Parallelism for Multicore Processors

Wireless Networks and Computational Intelligence, p.426-435

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Design of a Low Power 11T-1MTJ Non-Volatile SRAM Cell with Half-Select Free Operation

2020 IEEE 17th India Council International Conference (INDICON), 2020, p.1-5

2020

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Twin-Coupled Sense Amplifier to improve margin in 1T-1MTJ based MRAM array

2020 24th International Symposium on VLSI Design and Test (VDAT), 2020, p.1-4

2020

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Design of a Robust Logic Gate using Magnetic Tunnel Junction

2019 IEEE 16th India Council International Conference (INDICON), 2019, p.1-4

2019

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An Energy Efficient Multilevel Reconfigurable parallel Cache Architecture for Embedded Multicore Processors

2019 International Conference on Electrical, Electronics and Computer Engineering (UPCON), 2019, p.1-6

2019

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A Dual-Mode In-Memory Computing Unit Using Spin Hall-Assisted MRAM for Data-Intensive Applications

Energy Efficient Ternary Multi-trit Multiplier Design Using Novel Adders

Design of a STT-MTJ Based Random-Access Memory With In-situ Processing for Data-Intensive Applications

An optimal delay aware task assignment scheme for wireless SDN networked edge cloudlets

Design of a novel CMOS/MTJ-based multibit SRAM cell with low store energy for IoT applications

Energy-efficient data retention in D flip-flops using STT-MTJ

Design of a tunable delay line with on-chip calibration to generate process-invariant PWM signal for in-memory computing

E-SATS: An Efficient and Simple Time Synchronization Protocol for Cluster- Based Wireless Sensor Networks

Design of a Low Power Approximate Adder based on Magnetic Tunnel Junction for Image Processing Applications

Design of an MTJ/CMOS-Based Asynchronous System for Ultra-Low Power Energy Autonomous Applications

A low power high speed MTJ based non-volatile SRAM cell for energy harvesting based IoT applications

Integrated Cooperative Synchronization for Wireless Sensor Networks

An efficient adaptive block pinning for multicore architectures

An exploration of neuromorphic systems and related design issues/challenges in dark silicon era

A testbed validated simple time synchronization protocol for clustered wireless sensor networks for IoT

A Novel Architecture for FPGA Implementation of Otsu's Global Automatic Image Thresholding Algorithm

Study of Various Factors Affecting Performance of Multi-Core Processors

Register Allocation For Fine Grain Threads On Multicore Processor

Global Scheduling Heuristics for Multicore Architecture

Design of In-Memory Computing Enabled SRAM Macro

Compiler Driven Inter Block Parallelism for Multicore Processors

Design of a Low Power 11T-1MTJ Non-Volatile SRAM Cell with Half-Select Free Operation

Twin-Coupled Sense Amplifier to improve margin in 1T-1MTJ based MRAM array

Design of a Robust Logic Gate using Magnetic Tunnel Junction

An Energy Efficient Multilevel Reconfigurable parallel Cache Architecture for Embedded Multicore Processors

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