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A High-Speed Two-Cell BCH Decoder for Error Correcting in MLC nor Flash Memories

IEEE transactions on circuits and systems. II, Express briefs, 2009-11, Vol.56 (11), p.865-869

2009

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Low Latency High Throughout Circular Asynchronous FIFO

Tsinghua science and technology, 2008-12, Vol.13 (6), p.812-816

2008

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a new type of high-performance low-power low clock-swing TSPC flip-flop

2007 7th International Conference on ASIC, 2007, p.130-133

2007

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A high efficiency CMOS charge pump for low voltage operation

2009 IEEE 8th International Conference on ASIC, 2009, p.320-323

2009

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Embedded high-speed BCH decoder for new-generation NOR flash memories

2009 IEEE Custom Integrated Circuits Conference, 2009, p.195-198

2009

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Low power inductor-less pulse UWB transceiver

2009 IEEE International Symposium on Circuits and Systems (ISCAS), 2009, p.2093-2096

2009

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Design of a fully pipelined single-precision floating-point unit

2007 7th International Conference on ASIC, 2007, p.60-63

2007

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A NOVEL SCHEME OF IMPLEMENTING HIGH-SPEED HIGH-PROBABILITY-RESOLUTION DIGITAL AWGN GENERATORS

Journal of circuits, systems, and computers, 2007-04, Vol.16 (2), p.211-219

2007

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A fully integrated CMOS UWB transmitter

2007 7th International Conference on ASIC, 2007, p.372-374

2007

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A fully-integrated CMOS UWB transceiver for ultra-low-power short-range application

International journal of circuit theory and applications, 2011-07, Vol.39 (7), p.783-790

2011

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A transition entropy area estimation method for combinational circuits

ASIC, 2003. Proceedings. 5th International Conference on, 2003, Vol.1, p.63-66 Vol.1

2003

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A novel built-in CMOS sensor for on-line thermal monitoring of VLSI circuits

ASIC, 2003. Proceedings. 5th International Conference on, 2003, Vol.2, p.1345-1348 Vol.2

2003

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Power analysis and optimization methods of the pipelined array multiplier

ASIC, 2003. Proceedings. 5th International Conference on, 2003, Vol.2, p.1231-1234 Vol.2

2003

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Physical implementation and test of energy recovery circuit

ASIC, 2003. Proceedings. 5th International Conference on, 2003, Vol.2, p.1205-1208 Vol.2

2003

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The design of an improved low-power voltage testing and protection circuit

ASIC, 2003. Proceedings. 5th International Conference on, 2003, Vol.1, p.530-533 Vol.1

2003

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LOW CLOCK-SWING TSPC FLIP-FLOPS FOR LOW-POWER APPLICATIONS

Journal of circuits, systems, and computers, 2009-02, Vol.18 (1), p.121-131

2009

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Asynchronous trigger reception algorithm for low-power UWB system

2010 IEEE International Conference on Ultra-Wideband, 2010, Vol.2, p.1-4

2010

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An on-chip high-speed 4-bit BCH decoder in MLC NOR flash memories

2009 IEEE Asian Solid-State Circuits Conference, 2009, p.229-232

2009

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Low-latency array architecture for telescopic-search-based motion estimation

Electronics letters, 2000-08, Vol.36 (16), p.1-1

2000

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Motion estimation using low-bit oriented edge image for DCT-based video compression

Electronics letters, 2001-04, Vol.37 (8), p.1-1

2001

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Improved energy recovery logic for low power computation

IEEE 2002 International Conference on Communications, Circuits and Systems and West Sino Expositions, 2002, Vol.2, p.1740-1743 vol.2

2002

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An MBOK-UWB SoC transceiver in 0.181μm CMOS technology

2007 7th International Conference on ASIC, 2007, p.830-833

2007

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Low-power motion-estimation architecture based on a novel early-jump-out technique

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 2001, Vol.5, p.187-190 vol. 5

2001

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Low-latency array architecture for telescopic-search-based motion estimation

Electronics letters, 2000-08, Vol.36 (16), p.1365-1366

2000

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Motion estimation using low-bit oriented edge image for DCT-based video compression

Electronics letters, 2001-04, Vol.37 (8), p.494-495

2001

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A High-Speed Two-Cell BCH Decoder for Error Correcting in MLC nor Flash Memories

Low Latency High Throughout Circular Asynchronous FIFO

a new type of high-performance low-power low clock-swing TSPC flip-flop

A high efficiency CMOS charge pump for low voltage operation

Embedded high-speed BCH decoder for new-generation NOR flash memories

Low power inductor-less pulse UWB transceiver

Design of a fully pipelined single-precision floating-point unit

A NOVEL SCHEME OF IMPLEMENTING HIGH-SPEED HIGH-PROBABILITY-RESOLUTION DIGITAL AWGN GENERATORS

A fully integrated CMOS UWB transmitter

A fully-integrated CMOS UWB transceiver for ultra-low-power short-range application

A transition entropy area estimation method for combinational circuits

A novel built-in CMOS sensor for on-line thermal monitoring of VLSI circuits

Power analysis and optimization methods of the pipelined array multiplier

Physical implementation and test of energy recovery circuit

The design of an improved low-power voltage testing and protection circuit

LOW CLOCK-SWING TSPC FLIP-FLOPS FOR LOW-POWER APPLICATIONS

Asynchronous trigger reception algorithm for low-power UWB system

An on-chip high-speed 4-bit BCH decoder in MLC NOR flash memories

Low-latency array architecture for telescopic-search-based motion estimation

Motion estimation using low-bit oriented edge image for DCT-based video compression

Improved energy recovery logic for low power computation

An MBOK-UWB SoC transceiver in 0.181μm CMOS technology

Low-power motion-estimation architecture based on a novel early-jump-out technique

Low-latency array architecture for telescopic-search-based motion estimation

Motion estimation using low-bit oriented edge image for DCT-based video compression

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