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Digital Twin Development: An Introduction to Simcenter Amesim

1, 2023

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VEDLIoT: Very Efficient Deep Learning in IoT

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022, p.963-968

2022

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A massively parallel architecture for self-organizing feature maps

IEEE transactions on neural networks, 2003-09, Vol.14 (5), p.1110-1121

2003

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ULSI architectures for artificial neural networks

IEEE MICRO, 2002-05, Vol.22 (3), p.10-19

Ruckert, U.

2002

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A ray-tracing approach for simulating recognition abilities of active infrared sensor arrays

IEEE sensors journal, 2004-04, Vol.4 (2), p.237-247

2004

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Design Optimizations for Tiled Partially Reconfigurable Systems

IEEE transactions on very large scale integration (VLSI) systems, 2011-06, Vol.19 (6), p.1048-1061

2011

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VLSI implementation of an associative memory based on distributed storage of information

Lecture notes in computer science, 2005, Vol.412, p.267-276

2005

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Real-time implementation of digital coherent detection

2009 35th European Conference on Optical Communication, 2009, p.1-4

2009

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A Modified Multiple Depth First Search Algorithm for Grid Mapping Using Mini-Robots Khepera

Journal of computing science and engineering : JCSE, 2008-12, Vol.2 (4), p.321-338

2008

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Analyzing microarray data using quantitative association rules

Bioinformatics, 2005-09, Vol.21 (suppl-2), p.ii123-ii129

2005

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FPGA-based realization of self-optimizing drive-controllers

2009 35th Annual Conference of IEEE Industrial Electronics, 2009, p.2848-2853

2009

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Adapted Transfer of Distance Measures for Quantitative Structure-Activity Relationships and Data-Driven Selection of Source Datasets

Computer journal, 2013-03, Vol.56 (3), p.274-288

2013

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Fault-tolerance of basis function networks using tensor product stabilizers

2005 IEEE International Conference on Systems, Man and Cybernetics, 2005, Vol.3, p.2144-2149 Vol. 3

2005

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REPLICA: a bitstream manipulation filter for module relocation in partial reconfigurable systems

19th IEEE International Parallel and Distributed Processing Symposium, 2005, p.8 pp.

2005

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A mapping strategy for resource-efficient network processing on multiprocessor SoCs

Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004, Vol.2, p.758-763 Vol.2

2004

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A TCMS-based architecture for GALS NoCs

2012 IEEE International Symposium on Circuits and Systems (ISCAS), 2012, p.2721-2724

2012

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Performance analysis of the nRF24L01 ultra-low-power transceiver in a multi-transmitter and multi-receiver scenario

2011 IEEE SENSORS Proceedings, 2011, p.1205-1208

2011

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Reduced oversampling rate for adaptive search based blind FD CD estimation

2013 18th OptoElectronics and Communications Conference held jointly with 2013 International Conference on Photonics in Switching (OECC/PS), 2013, p.1-2

2013

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Robustness of Radial Basis Functions

Computational Intelligence and Bioinspired Systems, 2005, p.264-271

2005

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Hardware Support for Dynamic Reconfiguration in Reconfigurable SoC Architectures

Field Programmable Logic and Application, 2004, p.842-846

2004

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Simultaneous determination of total hypericin and hyperforin in St. John's wort extracts by HPLC with electrochemical detection

Phytochemical analysis, 2007-05, Vol.18 (3), p.204-208

2007

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A reconfigurable neuroprocessor for self-organizing feature maps

Neurocomputing (Amsterdam), 2013-07, Vol.112, p.189-199

2013

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FPGA-in-the-loop-simulations for dynamically reconfigurable applications

2009 International Conference on Field-Programmable Technology, 2009, p.372-375

2009

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An experiment of subband spectral shaping in DFT-spread CO-OFDM systems

2013 18th OptoElectronics and Communications Conference held jointly with 2013 International Conference on Photonics in Switching (OECC/PS), 2013, p.1-2

2013

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ULSI architectures for artificial neural networks

Proceedings Ninth Euromicro Workshop on Parallel and Distributed Processing, 2001, p.436-442

Ruckert, U.

2001

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Digital Twin Development: An Introduction to Simcenter Amesim

VEDLIoT: Very Efficient Deep Learning in IoT

A massively parallel architecture for self-organizing feature maps

ULSI architectures for artificial neural networks

A ray-tracing approach for simulating recognition abilities of active infrared sensor arrays

Design Optimizations for Tiled Partially Reconfigurable Systems

VLSI implementation of an associative memory based on distributed storage of information

Real-time implementation of digital coherent detection

A Modified Multiple Depth First Search Algorithm for Grid Mapping Using Mini-Robots Khepera

Analyzing microarray data using quantitative association rules

FPGA-based realization of self-optimizing drive-controllers

Adapted Transfer of Distance Measures for Quantitative Structure-Activity Relationships and Data-Driven Selection of Source Datasets

Fault-tolerance of basis function networks using tensor product stabilizers

REPLICA: a bitstream manipulation filter for module relocation in partial reconfigurable systems

A mapping strategy for resource-efficient network processing on multiprocessor SoCs

A TCMS-based architecture for GALS NoCs

Performance analysis of the nRF24L01 ultra-low-power transceiver in a multi-transmitter and multi-receiver scenario

Reduced oversampling rate for adaptive search based blind FD CD estimation

Robustness of Radial Basis Functions

Hardware Support for Dynamic Reconfiguration in Reconfigurable SoC Architectures

Simultaneous determination of total hypericin and hyperforin in St. John's wort extracts by HPLC with electrochemical detection

A reconfigurable neuroprocessor for self-organizing feature maps

FPGA-in-the-loop-simulations for dynamically reconfigurable applications

An experiment of subband spectral shaping in DFT-spread CO-OFDM systems

ULSI architectures for artificial neural networks

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