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P-428 Fertility outcomes following treatment of chronic endometritis: a systematic review and meta-analysis

Human reproduction (Oxford), 2022-06, Vol.37 (Supplement_1)

2022

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P-614 The use of home ovulation prediction kits (OPKs) in true natural cycle frozen embryo transfer (NC FET)

Human reproduction (Oxford), 2024-07, Vol.39 (Supplement_1)

2024

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IC bridge fault modeling for IP blocks using neural network-based VHDL saboteurs

IEEE transactions on computers, 2003-10, Vol.52 (10), p.1285-1297

2003

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On the use of VHDL as a multi-valued logic simulator

Proceedings / International Symposium on Multiple-Valued Logic, 1996, p.110-115

Rozon, C.

1996

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Detection of polymorphisms and mutations in the porphobilinogen deaminase gene by nonisotopic SSCP

Clinical chemistry (Baltimore, Md.), 1994-10, Vol.40 (10), p.1982-1983

1994

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Realization of a three-valued logic built-in testing structure

IEEE journal of solid-state circuits, 1990-06, Vol.25 (3), p.814-820

1990

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VHDL modelling and analysis of fault secure systems

Proceedings Design, Automation and Test in Europe, 1998, p.148-152

1998

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Comprehensive defect analysis and defect coverage of CMOS circuits

Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223), 1998, p.84-92

1998

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Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS ＆ BiCMOS Circuits

VLSI Design, 1994-12, Vol.1994, p.l261-276

1994

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Accurate CMOS bridge fault modeling with neural network-based VHDL saboteurs

Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design, 2001, p.531-536

2001

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Fault security analysis of CMOS VLSI circuits using defect-injectable VHDL models

Integration (Amsterdam), 2002-11, Vol.32 (1), p.77-97

2002

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Testability analysis of CMOS ternary circuits

[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic, 1991, p.158-165

1991

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Automated defect to fault translation for ASIC standard cell libraries

2001 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (IEEE Cat. No.01CH37233), 2001, Vol.1, p.291-294 vol.1

2001

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Test pattern generation for CMOS ternary logic

International journal of electronics, 1988-08, Vol.65 (2), p.155-163

1988

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Comparing defect coverage for current-mode logic and CMOS VLSI cells

ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445), 2000, Vol.1, p.429-432 vol.1

2000

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VHDL modelling and analysis of fault secure systems

Design, Automation, and Test in Europe: Proceedings of the conference on Design, automation and test in Europe; 23-26 Feb. 1998, 1998, p.148-152

1998

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Ultra low leakage structures for logic circuits using symmetric and asymmetric FinFETs

10th IEEE International NEWCAS Conference, 2012, p.385-388

2012

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Improved VLSI design for decoding concatenated codes comprising an irreducible cyclic code and a Reed-Solomon Code

Information Theory and Applications II, 2005, p.104-110

2005

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The effect of the learning curve on the outcome of laparoscopic treatment for gastroesophageal reflux

Surgical laparoscopy, endoscopy & percutaneous techniques, 1999-12, Vol.9 (6), p.375-381

1999

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A CNFET-based characterization framework for digital circuits

2011 18th IEEE International Conference on Electronics, Circuits, and Systems, 2011, p.681-684

2011

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Gate level static power estimation in UDSM processes

2008 International Conference on Microelectronics, 2008, p.212-215

2008

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Static leakage current estimation of on-the-fly generated IP logic blocks

2009 4th IEEE Conference on Industrial Electronics and Applications, 2009, p.133-138

2009

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A new subthreshold leakage model for NMOS transistor stacks

2007 IEEE Northeast Workshop on Circuits and Systems, 2007, p.972-975

2007

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Accurate Total Static Leakage Current Estimation in Transistor Stacks

IEEE International Conference on Computer Systems and Applications, 2006, 2006, p.262-265

2006

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Testability analysis and fault modeling of BiCMOS circuits

Journal of electronic testing, 1992-08, Vol.3 (3), p.207-217

1992

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P-428 Fertility outcomes following treatment of chronic endometritis: a systematic review and meta-analysis

P-614 The use of home ovulation prediction kits (OPKs) in true natural cycle frozen embryo transfer (NC FET)

IC bridge fault modeling for IP blocks using neural network-based VHDL saboteurs

On the use of VHDL as a multi-valued logic simulator

Detection of polymorphisms and mutations in the porphobilinogen deaminase gene by nonisotopic SSCP

Realization of a three-valued logic built-in testing structure

VHDL modelling and analysis of fault secure systems

Comprehensive defect analysis and defect coverage of CMOS circuits

Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS ＆ BiCMOS Circuits

Accurate CMOS bridge fault modeling with neural network-based VHDL saboteurs

Fault security analysis of CMOS VLSI circuits using defect-injectable VHDL models

Testability analysis of CMOS ternary circuits

Automated defect to fault translation for ASIC standard cell libraries

Test pattern generation for CMOS ternary logic

Comparing defect coverage for current-mode logic and CMOS VLSI cells

VHDL modelling and analysis of fault secure systems

Ultra low leakage structures for logic circuits using symmetric and asymmetric FinFETs

Improved VLSI design for decoding concatenated codes comprising an irreducible cyclic code and a Reed-Solomon Code

The effect of the learning curve on the outcome of laparoscopic treatment for gastroesophageal reflux

A CNFET-based characterization framework for digital circuits

Gate level static power estimation in UDSM processes

Static leakage current estimation of on-the-fly generated IP logic blocks

A new subthreshold leakage model for NMOS transistor stacks

Accurate Total Static Leakage Current Estimation in Transistor Stacks

Testability analysis and fault modeling of BiCMOS circuits

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