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SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors

Proceedings of the IEEE, 2010-02, Vol.98 (2), p.144-159

2010

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A design platform for 90-nm leakage reduction techniques

Annual ACM IEEE Design Automation Conference: Proceedings of the 42nd annual conference on Design automation; 13-17 June 2005, 2005, p.549-550

2005

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90nm low leakage SoC design techniques for wireless applications

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005, 2005, p.138-589 Vol. 1

2005

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Low power optimization for a 40nm RFCMOS wireless connectivity chip

2012 IEEE Faible Tension Faible Consommation, 2012, p.1-4

2012

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Practical and efficient SOC verification flow by reusing IP testcase and testbench

2012 International SoC Design Conference (ISOCC), 2012, p.175-178

2012

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Leakage Power Reduction Techniques applied to 90-nm SoC Application Processor

2006 IEEE International Conference on IC Design and Technology, 2006, p.1-2

2006

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Re-Using Clock Management Unit to implement Power Gating and Retention for Leakage Reduction at the 65-nm Technology Node

2007 IEEE International Conference on Integrated Circuit Design and Technology, 2007, p.1-2

2007

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A 65-nm Mobile Multimedia Applications Processor with an Adaptive Power Management Scheme to Compensate for Variations

2007 IEEE Symposium on VLSI Circuits, 2007, p.224-225

2007

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Solutions for logic and processor core design at the 45nm technology node & and below

2007 14th IEEE International Conference on Electronics, Circuits and Systems, 2007, p.923-926

2007

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A 1.0 ns 64-bits GaAs adder using quad tree algorithm

Proceedings of the Sixth Great Lakes Symposium on VLSI, 1996, p.24-28

1996

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A 1.0ns 64-bits GaAs Adder using Quad tree algorithm

Great Lakes Symposium on VLSI: Proceedings of the 6th Great Lakes Symposium on VLSI; 22-23 Mar. 1996, 1996

1996

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A Leakage Management System Based on Clock Gating Infrastructure for a 65-nm Digital Base-Band Modem Chip

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers, 2006, p.214-215

2006

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Barriers to Cervical Cancer Screening in Geneva (DEPIST Study)

Journal of lower genital tract disease, 2016-04, Vol.20 (2), p.135-138

2016

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SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors

A design platform for 90-nm leakage reduction techniques

90nm low leakage SoC design techniques for wireless applications

Low power optimization for a 40nm RFCMOS wireless connectivity chip

Practical and efficient SOC verification flow by reusing IP testcase and testbench

Leakage Power Reduction Techniques applied to 90-nm SoC Application Processor

Re-Using Clock Management Unit to implement Power Gating and Retention for Leakage Reduction at the 65-nm Technology Node

A 65-nm Mobile Multimedia Applications Processor with an Adaptive Power Management Scheme to Compensate for Variations

Solutions for logic and processor core design at the 45nm technology node & and below

A 1.0 ns 64-bits GaAs adder using quad tree algorithm

A 1.0ns 64-bits GaAs Adder using Quad tree algorithm

A Leakage Management System Based on Clock Gating Infrastructure for a 65-nm Digital Base-Band Modem Chip

Barriers to Cervical Cancer Screening in Geneva (DEPIST Study)

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