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FabScalar: Automating Superscalar Core Design

IEEE MICRO, 2012-05, Vol.32 (3), p.48-59

2012

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Control-Flow Decoupling: An Approach for Timely, Non-Speculative Branching

IEEE transactions on computers, 2015-08, Vol.64 (8), p.2182-2203

2015

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ZettaRAM: A Power-Scalable DRAM Alternative through Charge-Voltage Decoupling

IEEE transactions on computers, 2007-02, Vol.56 (2), p.147-160

2007

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Slipstream processors revisited: exploiting branch sets

2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), 2020, p.105-117

2020

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Post-Fabrication Microarchitecture

MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021, p.1270-1281

2021

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Post-Silicon Microarchitecture

IEEE computer architecture letters, 2020-01, Vol.19 (1), p.26-29

2020

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Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM

The Twelfth International Symposium on High-Performance Computer Architecture, 2006, 2006, p.155-165

2006

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AR-SMT: a microarchitectural approach to fault tolerance in microprocessors

Digest of Papers. Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing (Cat. No.99CB36352), 1999, p.84-91

Rotenberg, E.

1999

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FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template

2011 38th Annual International Symposium on Computer Architecture (ISCA), 2011, p.11-22

2011

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A unified view of non-monotonic core selection and application steering in heterogeneous chip multiprocessors

Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013, p.133-144

2013

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A unified view of non-monotonic core selection and application steering in heterogeneous chip multiprocessors

Proceedings of the 22nd international conference on Parallel architectures and compilation techniques, 2013, p.133-144

2013

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Trace cache: A low latency approach to high bandwidth instruction fetching

Proceedings of the annual International Symposium on Microarchitecture, 1996, p.24-34

1996

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A large, fast instruction window for tolerating cache misses

ACM SIGARCH Computer Architecture News, 2002-05, Vol.30 (2), p.59-70

2002

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Design-effort alloy: Boosting a highly tuned primary core with untuned alternate cores

2014 IEEE 32nd International Conference on Computer Design (ICCD), 2014, p.408-415

2014

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Control-Flow Decoupling

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012, p.329-340

2012

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H3 (Heterogeneity in 3D): A Logic-on-Logic 3D-Stacked Heterogeneous Multi-Core Processor

2017 IEEE International Conference on Computer Design (ICCD), 2017, p.145-152

2017

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Criticality-driven superscalar design space exploration

2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT), 2010, p.261-272

2010

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Trace processors

Proceedings of 30th Annual International Symposium on Microarchitecture, 1997, p.138-148

1997

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Coverage of a microarchitecture-level fault check regimen in a superscalar processor

2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN), 2008, p.1-10

2008

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Fast register consolidation and migration for heterogeneous multi-core processors

2016 IEEE 34th International Conference on Computer Design (ICCD), 2016, p.1-8

2016

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A large, fast instruction window for tolerating cache misses

Proceedings 29th Annual International Symposium on Computer Architecture, 2002, p.59-70

2002

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Assigning confidence to conditional branch predictions

Proceedings of the annual International Symposium on Microarchitecture, 1996, p.142-152

1996

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Adaptive mode control: A static-power-efficient cache design

ACM transactions on embedded computing systems, 2003-08, Vol.2 (3), p.347-372

2003

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Message from the Program Co-Chairs

2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06), 2006, p.x-x

2006

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Architectural Contesting

2009 IEEE 15th International Symposium on High Performance Computer Architecture, 2009, p.189-200

2009

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FabScalar: Automating Superscalar Core Design

Control-Flow Decoupling: An Approach for Timely, Non-Speculative Branching

ZettaRAM: A Power-Scalable DRAM Alternative through Charge-Voltage Decoupling

Slipstream processors revisited: exploiting branch sets

Post-Fabrication Microarchitecture

Post-Silicon Microarchitecture

Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM

AR-SMT: a microarchitectural approach to fault tolerance in microprocessors

FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template

A unified view of non-monotonic core selection and application steering in heterogeneous chip multiprocessors

A unified view of non-monotonic core selection and application steering in heterogeneous chip multiprocessors

Trace cache: A low latency approach to high bandwidth instruction fetching

A large, fast instruction window for tolerating cache misses

Design-effort alloy: Boosting a highly tuned primary core with untuned alternate cores

Control-Flow Decoupling

H3 (Heterogeneity in 3D): A Logic-on-Logic 3D-Stacked Heterogeneous Multi-Core Processor

Criticality-driven superscalar design space exploration

Trace processors

Coverage of a microarchitecture-level fault check regimen in a superscalar processor

Fast register consolidation and migration for heterogeneous multi-core processors

A large, fast instruction window for tolerating cache misses

Assigning confidence to conditional branch predictions

Adaptive mode control: A static-power-efficient cache design

Message from the Program Co-Chairs

Architectural Contesting

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