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Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks

IEEE journal of solid-state circuits, 1996-03, Vol.31 (3), p.456-465

1996

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IEEE_Xplore

Reducing Transistor Variability for High Performance Low Power Chips

IEEE MICRO, 2013-03, Vol.33 (2), p.18-26

2013

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IEEE_Xplore

An 800-MHz 1-μm CMOS pipelined 8-b adder using true single-phase clocked logic-flip-flops

IEEE journal of solid-state circuits, 1996-03, Vol.31 (3), p.401-409

1996

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The impact of transistor sizing on power efficiency in submicron CMOS circuits

IEEE journal of solid-state circuits, 1997-07, Vol.32 (7), p.1142-1145

1997

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IEEE_Xplore

A 2x load/store pipe for a low-power 1-GHz embedded processor

IEEE journal of solid-state circuits, 2003-11, Vol.38 (11), p.1857-1865

2003

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Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013, p.1-4

2013

Link zum Volltext
IEEE_Xplore

An 800-MHz 1-/spl mu/m CMOS pipelined 8-b adder using true single-phase clocked logic-flip-flops

IEEE journal of solid-state circuits, 1996-03, Vol.31 (3), p.401-409

1996

Link zum Volltext
IEEE_Xplore

An 800-MHz 1-mu m CMOS pipelined 8-b adder using true single-phaseclocked logic-flip-flops

IEEE journal of solid-state circuits, 1996-03, Vol.31 (3), p.401-409

1996

Link zum Volltext

Verfügbarkeit prüfen

A 2× load/store pipe for a low-power 1-GHz embedded processor

IEEE journal of solid-state circuits, 2003-11, Vol.38 (11), p.1857

2003

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A 2/spl times/ load/store pipe for a low-power 1-GHz embedded processor

IEEE journal of solid-state circuits, 2003-11, Vol.38 (11), p.1857-1865

2003

Link zum Volltext
IEEE_Xplore

An 800 MHz 1-micron CMOS pipelined 8-bit adder using true single-phase logic-flip-flops

Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, 1995, p.581-584

1995

Link zum Volltext
IEEE_Xplore

A glitch-free single-phase CMOS DFF for gigahertz applications

1994 IEEE International Symposium on Circuits and Systems (ISCAS), 1994, Vol.4, p.11-14 vol.4

1994

Link zum Volltext
IEEE_Xplore

A 2/spl times/ load/store pipe for a low-power 1GHz embedded processor

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC, 2003, p.340-341 vol.1

2003

Link zum Volltext
IEEE_Xplore

A highly integrated 65-nm SoC process with enhanced power/performance of digital and analog circuits

2012 International Electron Devices Meeting, 2012, p.14.4.1-14.4.4

2012

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IEEE_Xplore

A 375 MHz 1 /spl mu/m CMOS 8-bit multiplier

Digest of Technical Papers., Symposium on VLSI Circuits, 1995, p.13-14

1995

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A dual-issue floating-point coprocessor with SIMD architecture and fast 3D functions

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), 2002, Vol.1, p.414-415 vol.1

2002

Link zum Volltext
IEEE_Xplore

A dual-issue floating-point coprocessor with SIMD architecture and fast 3D functions

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), 2002, Vol.2, p.336-536

2002

Link zum Volltext
IEEE_Xplore

1.57 GHz asynchronous and 1.4 GHz dual-modulus 1.2 /spl mu/m CMOS prescalers

Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94, 1994, p.387-390

1994

Link zum Volltext
IEEE_Xplore

1.16 GHz dual-modulus 1.2 /spl mu/m CMOS prescaler

Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93, 1993, p.27.6.1-27.6.4

1993

Link zum Volltext
IEEE_Xplore

A 1 GHz power efficient single chip multiprocessor system for broadband networking applications

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185), 2001, p.107-110

2001

Link zum Volltext
IEEE_Xplore

Effects of hip arthroplasty followed by by inpatient rehabilitation on physical function and quality of life

Praxis (Bern. 1994), 2003-09, Vol.92 (37), p.1515

2003

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Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks

Reducing Transistor Variability for High Performance Low Power Chips

An 800-MHz 1-μm CMOS pipelined 8-b adder using true single-phase clocked logic-flip-flops

The impact of transistor sizing on power efficiency in submicron CMOS circuits

A 2x load/store pipe for a low-power 1-GHz embedded processor

Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias

An 800-MHz 1-/spl mu/m CMOS pipelined 8-b adder using true single-phase clocked logic-flip-flops

An 800-MHz 1-mu m CMOS pipelined 8-b adder using true single-phaseclocked logic-flip-flops

A 2× load/store pipe for a low-power 1-GHz embedded processor

A 2/spl times/ load/store pipe for a low-power 1-GHz embedded processor

An 800 MHz 1-micron CMOS pipelined 8-bit adder using true single-phase logic-flip-flops

A glitch-free single-phase CMOS DFF for gigahertz applications

A 2/spl times/ load/store pipe for a low-power 1GHz embedded processor

A highly integrated 65-nm SoC process with enhanced power/performance of digital and analog circuits

A 375 MHz 1 /spl mu/m CMOS 8-bit multiplier

A dual-issue floating-point coprocessor with SIMD architecture and fast 3D functions

A dual-issue floating-point coprocessor with SIMD architecture and fast 3D functions

1.57 GHz asynchronous and 1.4 GHz dual-modulus 1.2 /spl mu/m CMOS prescalers

1.16 GHz dual-modulus 1.2 /spl mu/m CMOS prescaler

A 1 GHz power efficient single chip multiprocessor system for broadband networking applications

Effects of hip arthroplasty followed by by inpatient rehabilitation on physical function and quality of life

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