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SET Characterization and Mitigation in 65-nm CMOS Test Structures

IEEE transactions on nuclear science, 2012-08, Vol.59 (4), p.851-859

2012

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Radiation-induced multi-bit upsets in SRAM-based FPGAs

IEEE transactions on nuclear science, 2005-12, Vol.52 (6), p.2455-2461

2005

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Design and Layout Effects on SET Propagation in 90-nm ASIC and FPGA Test Structures

IEEE transactions on nuclear science, 2010-12, Vol.57 (6), p.3716-3724

2010

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New Methodologies for SET Characterization and Mitigation in Flash-Based FPGAs

IEEE transactions on nuclear science, 2007-12, Vol.54 (6), p.2512-2524

2007

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Configuration and Routing Effects on the SET Propagation in Flash-Based FPGAs

IEEE transactions on nuclear science, 2008-12, Vol.55 (6), p.3328-3335

2008

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SEE Characterization of the New RTAX-DSP (RTAX-D) Antifuse-Based FPGA

IEEE transactions on nuclear science, 2010-12, Vol.57 (6), p.3537-3546

2010

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Predicting error rate for microprocessor-based digital architectures through C.E.U. (Code Emulating Upsets) injection

IEEE transactions on nuclear science, 2000-12, Vol.47 (6), p.2405-2411

2000

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Total-Ionizing Dose and Single-Event Effect Test Results of Analog and Mixed Signal Devices from Analog Devices

2018 IEEE Nuclear & Space Radiation Effects Conference (NSREC 2018), 2018, p.1-8

2018

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Investigation of Low Dose Rate and Bias Conditions on the Total Dose Tolerance of a CMOS Flash-Based FPGA

IEEE transactions on nuclear science, 2012-02, Vol.59 (1), p.134-143

2012

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Comparison of Dual-Rail and TMR Logic Cost Effectiveness and Suitability for FPGAs With Reconfigurable SEU Tolerance

IEEE transactions on nuclear science, 2009-02, Vol.56 (1), p.214-219

2009

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Dynamic testing of Xilinx Virtex-II field programmable gate array (FPGA) input/output blocks (IOBs)

IEEE transactions on nuclear science, 2004-12, Vol.51 (6), p.3469-3474

2004

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New Reprogrammable and Non-Volatile Radiation Tolerant FPGA: RTA3P

2008 IEEE Aerospace Conference, 2008, p.1-11

2008

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Characterization of Upset-Induced Degradation of Error-Mitigated High-Speed I/O's Using Fault Injection on SRAM Based FPGAs

IEEE transactions on nuclear science, 2006-08, Vol.53 (4), p.2076-2083

2006

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Complex upset mitigation applied to a Re-configurable embedded processor

IEEE transactions on nuclear science, 2005-12, Vol.52 (6), p.2468-2474

2005

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Estimating error rates in processor-based architectures

IEEE transactions on nuclear science, 2001-10, Vol.48 (5), p.1680-1687

2001

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Compendium of Single Event Effects Radiation Test Results from Ball Aerospace & Technologies Corp

2013 IEEE Radiation Effects Data Workshop (REDW), 2013, p.1-5

2013

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SET characterization and mitigation in RTAX-S antifuse FPGAs

2009 IEEE Aerospace conference, 2009, p.1-14

2009

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Validation of an SEU simulation technique for a complex processor: PowerPC7400

IEEE transactions on nuclear science, 2002-12, Vol.49 (6), p.3156-3162

2002

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New Reprogrammable and Non-Volatile Radiation-Tolerant Fpga : Rt Proasic®3

Rezgui, Sana

2010

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New Methodology for Simulation of Soft Errors in Digital Processors

Journal of spacecraft and rockets, 2002-07, Vol.39 (4), p.495-500

2002

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Synthesis of an 8051-Like Micro-Controller Tolerant to Transient Faults

Journal of electronic testing, 2001-04, Vol.17 (2), p.149

2001

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SET characterization & mitigation in 65-nm test structures

2011 12th European Conference on Radiation and Its Effects on Components and Systems, 2011, p.213-221

2011

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Heavy ion SEE testing of Xilinx one-time programmable configuration PROMs

2004 IEEE Radiation Effects Data Workshop (IEEE Cat. No.04TH8774), 2004, p.72-78

2004

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A single-chip supervised partial self-reconfigurable architecture for software defined radio

Proceedings International Parallel and Distributed Processing Symposium, 2003, p.7 pp.

2003

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MAV-DTLS toward Security Enhancement of the UAV-GCS Communication

2020 IEEE 92nd Vehicular Technology Conference (VTC2020-Fall), 2020, p.1-5

2020

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SET Characterization and Mitigation in 65-nm CMOS Test Structures

Radiation-induced multi-bit upsets in SRAM-based FPGAs

Design and Layout Effects on SET Propagation in 90-nm ASIC and FPGA Test Structures

New Methodologies for SET Characterization and Mitigation in Flash-Based FPGAs

Configuration and Routing Effects on the SET Propagation in Flash-Based FPGAs

SEE Characterization of the New RTAX-DSP (RTAX-D) Antifuse-Based FPGA

Predicting error rate for microprocessor-based digital architectures through C.E.U. (Code Emulating Upsets) injection

Total-Ionizing Dose and Single-Event Effect Test Results of Analog and Mixed Signal Devices from Analog Devices

Investigation of Low Dose Rate and Bias Conditions on the Total Dose Tolerance of a CMOS Flash-Based FPGA

Comparison of Dual-Rail and TMR Logic Cost Effectiveness and Suitability for FPGAs With Reconfigurable SEU Tolerance

Dynamic testing of Xilinx Virtex-II field programmable gate array (FPGA) input/output blocks (IOBs)

New Reprogrammable and Non-Volatile Radiation Tolerant FPGA: RTA3P

Characterization of Upset-Induced Degradation of Error-Mitigated High-Speed I/O's Using Fault Injection on SRAM Based FPGAs

Complex upset mitigation applied to a Re-configurable embedded processor

Estimating error rates in processor-based architectures

Compendium of Single Event Effects Radiation Test Results from Ball Aerospace & Technologies Corp

SET characterization and mitigation in RTAX-S antifuse FPGAs

Validation of an SEU simulation technique for a complex processor: PowerPC7400

New Reprogrammable and Non-Volatile Radiation-Tolerant Fpga : Rt Proasic®3

New Methodology for Simulation of Soft Errors in Digital Processors

Synthesis of an 8051-Like Micro-Controller Tolerant to Transient Faults

SET characterization & mitigation in 65-nm test structures

Heavy ion SEE testing of Xilinx one-time programmable configuration PROMs

A single-chip supervised partial self-reconfigurable architecture for software defined radio

MAV-DTLS toward Security Enhancement of the UAV-GCS Communication

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