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Identification and classification of single-event upsets in the configuration memory of SRAM-based FPGAs

IEEE transactions on nuclear science, 2003-12, Vol.50 (6), p.2088-2094

2003

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A new hybrid fault detection technique for systems-on-a-chip

IEEE transactions on computers, 2006-02, Vol.55 (2), p.185-198

2006

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Exploiting circuit emulation for fast hardness evaluation

IEEE transactions on nuclear science, 2001-12, Vol.48 (6), p.2210-2216

2001

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An Effective Technique for the Automatic Generation of Diagnosis-Oriented Programs for Processor Cores

IEEE transactions on computer-aided design of integrated circuits and systems, 2008-03, Vol.27 (3), p.570-574

2008

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Simulation-based analysis of SEU effects in SRAM-based FPGAs

IEEE transactions on nuclear science, 2004-12, Vol.51 (6), p.3354-3359

2004

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Coping with SEUs/SETs in microprocessors by means of low-cost solutions: a comparison study

IEEE transactions on nuclear science, 2002-06, Vol.49 (3), p.1491-1495

2002

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Impact of data cache memory on the single event upset-induced error rate of microprocessors

IEEE transactions on nuclear science, 2003-12, Vol.50 (6), p.2101-2106

2003

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Automatic test generation for verifying microprocessors

IEEE potentials, 2005-02, Vol.24 (1), p.34-37

2005

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On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs

Design, Automation and Test in Europe, 2005, p.1290-1295

2005

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RT-level ITC'99 benchmarks and first ATPG results

IEEE design & test of computers, 2000-07, Vol.17 (3), p.44-53

2000

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Automatic test program generation: a case study

IEEE design & test of computers, 2004-03, Vol.21 (2), p.102-109

2004

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Test Program Generation for Communication Peripherals in Processor-Based SoC Devices

IEEE design & test of computers, 2009-03, Vol.26 (2), p.52-63

2009

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An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers

2008 Design, Automation and Test in Europe, 2008, p.194-199

2008

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An accurate analysis of the effects of soft errors in the instruction and data caches of a pipelined microprocessor

2003 Design, Automation and Test in Europe Conference and Exhibition, 2003, p.602-607

2003

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System-in-package testing: problems and solutions

IEEE design & test of computers, 2006-05, Vol.23 (3), p.203-211

2006

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A new software-based technique for low-cost fault-tolerant application

Annual Reliability and Maintainability Symposium, 2003, 2003, p.25-28

2003

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On the Generation of Functional Test Programs for the Cache Replacement Logic

2009 Asian Test Symposium, 2009, p.418-423

2009

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Improved software-based processor control-flow errors detection technique

Annual Reliability and Maintainability Symposium, 2005. Proceedings, 2005, p.583-589

2005

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Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA

Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004, Vol.1, p.584-589 Vol.1

2004

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A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips

2009 Design, Automation & Test in Europe Conference & Exhibition, 2009, p.352-357

2009

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A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions

26th IEEE VLSI Test Symposium (vts 2008), 2008, p.389-394

2008

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On the generation of test programs for chip multi-thread computer architectures

2008 IEEE International Test Conference, 2008, p.1-1

2008

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Early, accurate dependability analysis of CAN-based networked systems

IEEE design & test of computers, 2006-01, Vol.23 (1), p.38-45

2006

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GALLO: a genetic algorithm for floorplan area optimization

IEEE transactions on computer-aided design of integrated circuits and systems, 1996-08, Vol.15 (8), p.943-951

1996

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On the transformation of manufacturing test sets into on-line test sets for microprocessors

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005, p.494-502

2005

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Identification and classification of single-event upsets in the configuration memory of SRAM-based FPGAs

A new hybrid fault detection technique for systems-on-a-chip

Exploiting circuit emulation for fast hardness evaluation

An Effective Technique for the Automatic Generation of Diagnosis-Oriented Programs for Processor Cores

Simulation-based analysis of SEU effects in SRAM-based FPGAs

Coping with SEUs/SETs in microprocessors by means of low-cost solutions: a comparison study

Impact of data cache memory on the single event upset-induced error rate of microprocessors

Automatic test generation for verifying microprocessors

On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs

RT-level ITC'99 benchmarks and first ATPG results

Automatic test program generation: a case study

Test Program Generation for Communication Peripherals in Processor-Based SoC Devices

An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers

An accurate analysis of the effects of soft errors in the instruction and data caches of a pipelined microprocessor

System-in-package testing: problems and solutions

A new software-based technique for low-cost fault-tolerant application

On the Generation of Functional Test Programs for the Cache Replacement Logic

Improved software-based processor control-flow errors detection technique

Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA

A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips

A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions

On the generation of test programs for chip multi-thread computer architectures

Early, accurate dependability analysis of CAN-based networked systems

GALLO: a genetic algorithm for floorplan area optimization

On the transformation of manufacturing test sets into on-line test sets for microprocessors

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