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A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits

Journal of electronic testing, 2017-02, Vol.33 (1), p.25-36

2017

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VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things : 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017, Revised and Extended Selected Papers

1st ed. 2019., 2019

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Evaluating the radiation sensitivity of GPGPU caches: New algorithms and experimental results

Microelectronics and reliability, 2014-11, Vol.54 (11), p.2621-2628

2014

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A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores

Journal of electronic testing, 2016-04, Vol.32 (2), p.147-161

2016

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Microprocessor Testing: Functional Meets Structural Test

Journal of circuits, systems, and computers, 2017-08, Vol.26 (8), p.1740007

2017

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On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs

Design, Automation and Test in Europe, 2005, p.1290-1295

2005

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On the use of embedded debug features for permanent and transient fault resilience in microprocessors

Microprocessors and microsystems, 2012-07, Vol.36 (5), p.334-343

2012

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A Functional Approach for Testing the Reorder Buffer Memory

Journal of electronic testing, 2014-08, Vol.30 (4), p.469-481

2014

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Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug

IET computers & digital techniques, 2010-03, Vol.4 (2), p.104-113

2010

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Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption

Journal of low-power electronics, 2013-08, Vol.9 (2), p.253-263

2013

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Early Detection of Permanent Faults in DNNs Through the Application of Tensor-Related Metrics

2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS), 2024, p.13-18

2024

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Assessing Convolutional Neural Networks Reliability through Statistical Fault Injections

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2023, p.1-6

2023

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Software-Based Hardening Strategies for Neutron Sensitive FFT Algorithms on GPUs

IEEE transactions on nuclear science, 2014-08, Vol.61 (4), p.1874-1880

2014

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A New Hybrid Nonintrusive Error-Detection Technique Using Dual Control-Flow Monitoring

IEEE transactions on nuclear science, 2014-12, Vol.61 (6), p.3236-3243

2014

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TCC: GPGPU Architecture for Instruction Decoder and Control Flow Error Detection

2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS), 2024, p.104-109

2024

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Software-Based Testing for System Peripherals

Journal of electronic testing, 2012-04, Vol.28 (2), p.189-200

2012

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Observability solutions for in-field functional test of processor-based systems: A survey and quantitative test case evaluation

Microprocessors and microsystems, 2016-11, Vol.47, p.392-403

2016

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TREFU: An Online Error Detecting and Correcting Fault Tolerant GPGPU Architecture

2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2023, p.1-7

2023

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Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs

Journal of electronic testing, 2007-02, Vol.23 (1), p.47-54

2007

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On-line functionally untestable fault identification in embedded processor cores

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, p.1462-1467

2013

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A System-layer Infrastructure for SoC Diagnosis

Journal of electronic testing, 2007-10, Vol.23 (5), p.389-404

2007

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On the in-field functional testing of decode units in pipelined RISC processors

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014, p.299-304

2014

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GPGPUs: how to combine high computational power with high reliability

Proceedings of the conference on Design, Automation & Test in Europe, 2014, p.1-9

2014

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Increasing the Fault Coverage of Processor Devices during the Operational Phase Functional Test

Journal of electronic testing, 2014-06, Vol.30 (3), p.317-328

2014

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Exploiting circuit emulation for fast hardness evaluation

IEEE transactions on nuclear science, 2001-12, Vol.48 (6), p.2210-2216

2001

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A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits

VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things : 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017, Revised and Extended Selected Papers

Evaluating the radiation sensitivity of GPGPU caches: New algorithms and experimental results

A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores

Microprocessor Testing: Functional Meets Structural Test

On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs

On the use of embedded debug features for permanent and transient fault resilience in microprocessors

A Functional Approach for Testing the Reorder Buffer Memory

Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug

Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption

Early Detection of Permanent Faults in DNNs Through the Application of Tensor-Related Metrics

Assessing Convolutional Neural Networks Reliability through Statistical Fault Injections

Software-Based Hardening Strategies for Neutron Sensitive FFT Algorithms on GPUs

A New Hybrid Nonintrusive Error-Detection Technique Using Dual Control-Flow Monitoring

TCC: GPGPU Architecture for Instruction Decoder and Control Flow Error Detection

Software-Based Testing for System Peripherals

Observability solutions for in-field functional test of processor-based systems: A survey and quantitative test case evaluation

TREFU: An Online Error Detecting and Correcting Fault Tolerant GPGPU Architecture

Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs

On-line functionally untestable fault identification in embedded processor cores

A System-layer Infrastructure for SoC Diagnosis

On the in-field functional testing of decode units in pipelined RISC processors

GPGPUs: how to combine high computational power with high reliability

Increasing the Fault Coverage of Processor Devices during the Operational Phase Functional Test

Exploiting circuit emulation for fast hardness evaluation

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