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A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors

IEEE journal of solid-state circuits, 2020-01, Vol.55 (1), p.189-202

2020

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A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors

IEEE journal of solid-state circuits, 2020-10, Vol.55 (10), p.2790-2801

2020

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A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.494-496

2018

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A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices

Nature electronics, 2021-01, Vol.4 (1), p.81-90

2021

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A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips

IEEE journal of solid-state circuits, 2021-09, Vol.56 (9), p.2817-2831

2021

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A 0.5-V Real-Time Computational CMOS Image Sensor With Programmable Kernel for Feature Extraction

IEEE journal of solid-state circuits, 2021-05, Vol.56 (5), p.1588-1596

2021

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A 0.8 V Intelligent Vision Sensor With Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification

IEEE journal of solid-state circuits, 2023-11, Vol.58 (11), p.1-9

2023

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SG-Float: Achieving Memory Access and Computing Power Reduction Using Self-Gating Float in CNNs

ACM transactions on embedded computing systems, 2023-11, Vol.22 (6), p.1-22, Article 101

2023

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Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors

IEEE journal of solid-state circuits, 2020-01, Vol.55 (1), p.203-215

2020

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Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips

IEEE journal of solid-state circuits, 2022-02, Vol.57 (2), p.609-624

2022

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CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors

Nature electronics, 2019-09, Vol.2 (9), p.420-428

2019

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A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips

IEEE journal of solid-state circuits, 2023-03, Vol.58 (3), p.877-892

2023

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A Multimode Vision Sensor With Temporal Contrast Pixel and Column-Parallel Local Binary Pattern Extraction for Dynamic Depth Sensing Using Stereo Vision

IEEE journal of solid-state circuits, 2023-10, Vol.58 (10), p.1-11

2023

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FM-P2L: An Algorithm Hardware Co-design of Fixed-Point MSBs with Power-of-2 LSBs in CNN Accelerators

2023 IEEE 41st International Conference on Computer Design (ICCD), 2023, p.407-414

2023

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A 0.8 V Multimode Vision Sensor for Motion and Saliency Detection With Ping-Pong PWM Pixel

IEEE journal of solid-state circuits, 2021-08, Vol.56 (8), p.2516-2524

2021

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Bit-Serial Cache: Exploiting Input Bit Vector Repetition to Accelerate Bit-Serial Inference

2023 60th ACM/IEEE Design Automation Conference (DAC), 2023, p.1-6

2023

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Morphable CIM: Improving Operation Intensity and Depthwise Capability for SRAM-CIM Architecture

2023 60th ACM/IEEE Design Automation Conference (DAC), 2023, p.1-6

2023

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8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices

IEEE journal of solid-state circuits, 2023-01, Vol.58 (1), p.1-13

2023

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An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices

IEEE journal of solid-state circuits, 2024-01, Vol.59 (1), p.1-12

2024

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A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices

2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, Vol.65, p.1-3

2022

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A four-megabit compute-in-memory macro with eight-bit precision based on CMOS and resistive random-access memory for AI edge devices

Nature electronics, 2021-12, Vol.4 (12), p.921-930

2021

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24.5 A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning

2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, p.396-398

2019

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A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips

IEEE journal of solid-state circuits, 2024-01, Vol.59 (1), p.196-207

2024

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A Nonvolatile AI-Edge Processor With SLC-MLC Hybrid ReRAM Compute-in-Memory Macro Using Current-Voltage-Hybrid Readout Scheme

IEEE journal of solid-state circuits, 2024-01, Vol.59 (1), p.116-127

2024

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LV: Latency-Versatile Floating-Point Engine for High-Performance Deep Neural Networks

IEEE computer architecture letters, 2023-07, Vol.22 (2), p.1-4

2023

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A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors

A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors

A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors

A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices

A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips

A 0.5-V Real-Time Computational CMOS Image Sensor With Programmable Kernel for Feature Extraction

A 0.8 V Intelligent Vision Sensor With Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification

SG-Float: Achieving Memory Access and Computing Power Reduction Using Self-Gating Float in CNNs

Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors

Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips

CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors

A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips

A Multimode Vision Sensor With Temporal Contrast Pixel and Column-Parallel Local Binary Pattern Extraction for Dynamic Depth Sensing Using Stereo Vision

FM-P2L: An Algorithm Hardware Co-design of Fixed-Point MSBs with Power-of-2 LSBs in CNN Accelerators

A 0.8 V Multimode Vision Sensor for Motion and Saliency Detection With Ping-Pong PWM Pixel

Bit-Serial Cache: Exploiting Input Bit Vector Repetition to Accelerate Bit-Serial Inference

Morphable CIM: Improving Operation Intensity and Depthwise Capability for SRAM-CIM Architecture

8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices

An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices

A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices

A four-megabit compute-in-memory macro with eight-bit precision based on CMOS and resistive random-access memory for AI edge devices

24.5 A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning

A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips

A Nonvolatile AI-Edge Processor With SLC-MLC Hybrid ReRAM Compute-in-Memory Macro Using Current-Voltage-Hybrid Readout Scheme

LV: Latency-Versatile Floating-Point Engine for High-Performance Deep Neural Networks

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