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A brief introduction on contemporary High-Level Synthesis

2014 IEEE International Conference on IC Design & Technology, 2014, p.1-4

Haoxing Ren

2014

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Techniques for Fast Physical Synthesis

Proceedings of the IEEE, 2007-03, Vol.95 (3), p.573-599

2007

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Diffusion-Based Placement Migration With Application on Legalization

IEEE transactions on computer-aided design of integrated circuits and systems, 2007-12, Vol.26 (12), p.2158-2172

2007

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Introduction to the Special Issue on Machine Learning for CAD/EDA

ACM transactions on design automation of electronic systems, 2023-03, Vol.28 (2), p.1-2, Article 14

2023

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Invited- NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning

2021 58th ACM/IEEE Design Automation Conference (DAC), 2021, p.1291-1294

2021

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ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-12, Vol.39 (12), p.5083-5096

2020

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DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-04, Vol.40 (4), p.748-761

2021

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Invited Paper: VerilogEval: Evaluating Large Language Models for Verilog Code Generation

2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2023, p.1-8

2023

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GRANNITE: Graph Neural Network Inference for Transferable Power Estimation

2020 57th ACM/IEEE Design Automation Conference (DAC), 2020, p.1-6

2020

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History-based VLSI legalization using network flow

Design Automation Conference, 2010, p.286-291

2010

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Accelerating Chip Design With Machine Learning

IEEE MICRO, 2020-11, Vol.40 (6), p.23-32

2020

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RouteNet: Routability prediction for Mixed-Size Designs Using Convolutional Neural Network

2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2018, p.1-8

2018

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PRIMAL: Power Inference using Machine Learning

2019 56th ACM/IEEE Design Automation Conference (DAC), 2019, p.1-6

2019

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High Performance Graph Convolutional Networks with Applications in Testability Analysis

Proceedings of the 56th Annual Design Automation Conference 2019, 2019, p.1-6

2019

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GAN-Place: Advancing Open Source Placers to Commercial-quality Using Generative Adversarial Networks and Transfer Learning

ACM transactions on design automation of electronic systems, 2024-03, Vol.29 (2), p.1-17, Article 32

2024

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BoolGebra: Attributed Graph-Learning for Boolean Algebraic Manipulation

2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024, p.1-2

2024

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Opportunities for RTL and gate level simulation using GPUs

2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020, p.1-5

2020

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An Adversarial Active Sampling-Based Data Augmentation Framework for AI-Assisted Lithography Modeling

2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2023, p.1-9

2023

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ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks

2020 57th ACM/IEEE Design Automation Conference (DAC), 2020, p.1-6

2020

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Why are Graph Neural Networks Effective for EDA Problems?

2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2022, p.1-8

2022

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Low cost test point insertion without using extra registers for high performance design

2009 International Test Conference, 2009, p.1-8

2009

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Domain-Adapted LLMs for VLSI Design and Verification: A Case Study on Formal Verification

2024 IEEE 42nd VLSI Test Symposium (VTS), 2024, p.1-4

2024

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From RTL to CUDA: A GPU Acceleration Flow for RTL Simulation with Batch Stimulus

Proceedings of the 51st International Conference on Parallel Processing, 2022, p.1-12

2022

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DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement

Proceedings of the 56th Annual Design Automation Conference 2019, 2019, p.1-6

2019

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Sensitivity guided net weighting for placement-driven synthesis

IEEE transactions on computer-aided design of integrated circuits and systems, 2005-05, Vol.24 (5), p.711-721

2005

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A brief introduction on contemporary High-Level Synthesis

Techniques for Fast Physical Synthesis

Diffusion-Based Placement Migration With Application on Legalization

Introduction to the Special Issue on Machine Learning for CAD/EDA

Invited- NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning

ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement

Invited Paper: VerilogEval: Evaluating Large Language Models for Verilog Code Generation

GRANNITE: Graph Neural Network Inference for Transferable Power Estimation

History-based VLSI legalization using network flow

Accelerating Chip Design With Machine Learning

RouteNet: Routability prediction for Mixed-Size Designs Using Convolutional Neural Network

PRIMAL: Power Inference using Machine Learning

High Performance Graph Convolutional Networks with Applications in Testability Analysis

GAN-Place: Advancing Open Source Placers to Commercial-quality Using Generative Adversarial Networks and Transfer Learning

BoolGebra: Attributed Graph-Learning for Boolean Algebraic Manipulation

Opportunities for RTL and gate level simulation using GPUs

An Adversarial Active Sampling-Based Data Augmentation Framework for AI-Assisted Lithography Modeling

ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks

Why are Graph Neural Networks Effective for EDA Problems?

Low cost test point insertion without using extra registers for high performance design

Domain-Adapted LLMs for VLSI Design and Verification: A Case Study on Formal Verification

From RTL to CUDA: A GPU Acceleration Flow for RTL Simulation with Batch Stimulus

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement

Sensitivity guided net weighting for placement-driven synthesis

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