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Deterministic Stellar BIST for Automotive ICs

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-08, Vol.39 (8), p.1699-1710

2020

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Optical Properties of Calcium Sodium Phosphate Glasses Doped With Strontium

Journal of physics. Conference series, 2020-03, Vol.1495 (1), p.12030

2020

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Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects

IEEE transactions on very large scale integration (VLSI) systems, 2008-01, Vol.16 (1), p.98-107

2008

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Switching Activity as a Test Compaction Heuristic for Transition Faults

IEEE transactions on very large scale integration (VLSI) systems, 2010-09, Vol.18 (9), p.1357-1361

2010

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Path Selection for Transition Path Delay Faults

IEEE transactions on very large scale integration (VLSI) systems, 2010-03, Vol.18 (3), p.401-409

2010

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Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-06, Vol.39 (6), p.1340-1345

2020

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An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction

IEEE transactions on very large scale integration (VLSI) systems, 2019-09, Vol.27 (9), p.2105-2118

2019

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On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-10, Vol.37 (10), p.2152-2165

2018

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Efficient Test Compression Configuration Selection

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-07, Vol.41 (7), p.2323-2336

2022

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Isometric Test Data Compression

IEEE transactions on computer-aided design of integrated circuits and systems, 2015-11, Vol.34 (11), p.1847-1859

2015

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Hydromagnetic Flow of Heat and Mass Transfer in a Nano Williamson Fluid Past a Vertical Plate With Thermal and Momentum Slip Effects: Numerical Study

Nonlinear engineering, 2019-01, Vol.8 (1), p.127-144

2019

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A Repair-for-Diagnosis Methodology for Logic Circuits

IEEE transactions on very large scale integration (VLSI) systems, 2018-11, Vol.26 (11), p.2254-2267

2018

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Forming multi-cycle tests for delay faults by concatenating broadside tests

2010 28th VLSI Test Symposium (VTS), 2010, p.51-56

2010

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Deterministic Stellar BIST for In-System Automotive Test

2018 IEEE International Test Conference (ITC), 2018, p.1-9

2018

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Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations

2022 IEEE 40th VLSI Test Symposium (VTS), 2022, p.1-7

2022

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Hazard-Based Detection Conditions for Improved Transition Path Delay Fault Coverage

IEEE transactions on computer-aided design of integrated circuits and systems, 2010-09, Vol.29 (9), p.1449-1453

2010

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Static Test Data Volume Reduction Using Complementation or Modulo- M Addition

IEEE transactions on very large scale integration (VLSI) systems, 2011-06, Vol.19 (6), p.1108-1112

2011

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On generating high quality tests based on cell functions

2015 IEEE International Test Conference (ITC), 2015, p.1-9

2015

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On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 2010-07, Vol.29 (7), p.1135-1140

2010

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At-speed scan test with low switching activity

2010 28th VLSI Test Symposium (VTS), 2010, p.177-182

2010

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Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Scan-Based Tests

IEEE transactions on very large scale integration (VLSI) systems, 2010-02, Vol.18 (2), p.333-337

2010

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Magnetic Field Effect on Tangent Hyperbolic Fluid towards Porous Plate with Suction/Injection

Research Journal of Science and Technology, 2017-10, Vol.9 (4), p.592-596

2017

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On Test Generation With Test Vector Improvement

IEEE transactions on computer-aided design of integrated circuits and systems, 2010-03, Vol.29 (3), p.502-506

2010

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SAT-Based Test Pattern Generation with Improved Dynamic Compaction

2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014, p.56-61

2014

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Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan Circuits

IEEE transactions on very large scale integration (VLSI) systems, 2011-02, Vol.19 (2), p.333-337

2011

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Deterministic Stellar BIST for Automotive ICs

Optical Properties of Calcium Sodium Phosphate Glasses Doped With Strontium

Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects

Switching Activity as a Test Compaction Heuristic for Transition Faults

Path Selection for Transition Path Delay Faults

Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run

An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction

On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits

Efficient Test Compression Configuration Selection

Isometric Test Data Compression

Hydromagnetic Flow of Heat and Mass Transfer in a Nano Williamson Fluid Past a Vertical Plate With Thermal and Momentum Slip Effects: Numerical Study

A Repair-for-Diagnosis Methodology for Logic Circuits

Forming multi-cycle tests for delay faults by concatenating broadside tests

Deterministic Stellar BIST for In-System Automotive Test

Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations

Hazard-Based Detection Conditions for Improved Transition Path Delay Fault Coverage

Static Test Data Volume Reduction Using Complementation or Modulo- M Addition

On generating high quality tests based on cell functions

On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits

At-speed scan test with low switching activity

Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Scan-Based Tests

Magnetic Field Effect on Tangent Hyperbolic Fluid towards Porous Plate with Suction/Injection

On Test Generation With Test Vector Improvement

SAT-Based Test Pattern Generation with Improved Dynamic Compaction

Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan Circuits

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