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Next-Generation Connectivity: A Holistic Review of Cooperative NOMA in Dynamic Vehicular Networks for Intelligent Transportation Systems

Scalable Computing. Practice and Experience, 2024-08, Vol.25 (5), p.3903-3924

2024

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Quantum-Dot Cellular Automata Technology for High-Speed High-Data-Rate Networks

Circuits, systems, and signal processing, 2019-11, Vol.38 (11), p.5236-5252

2019

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A 75 μW Two-Stage Op-Amp using 0.18μW CMOS Technology for High-Speed Operations

Acta physica Polonica, A, 2019-05, Vol.135 (5), p.1075-1077

2019

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SOI FinFET Based 10T SRAM Cell Design against Short Channel Effects

Acta physica Polonica, A, 2019-04, Vol.135 (4), p.702-704

2019

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50mv/Bar Sensitivity; Piezoresistive MEMS Altimeter Design for The Agricultural Drones

IOP conference series. Materials Science and Engineering, 2021-04, Vol.1145 (1), p.12088

2021

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Optimal Relay Selection Strategy for Efficient and Reliable Cluster-Based Cooperative Multi-Hop Transmission in Vehicular Communication

Cybernetics and systems, 2023-11, Vol.54 (8), p.1267-1289

2023

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A 9-bit pseudo-noise-based calibrated successive approximation ADC with differential/integral nonlinearity enhancement

Soft computing (Berlin, Germany), 2022-05, Vol.26 (9), p.4289-4294

2022

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Design and analysis of high performance 9 bit SAR ADC with SFDR 76.59

AIP Conference Proceedings, 2022, Vol.2418 (1)

2022

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Design of 14 bit current steering d/a converter with self-checking circuit for high speed iot applications

AIP Conference Proceedings, 2022, Vol.2424 (1)

2022

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Aggressive Development of Qunatum-Dot Cellular Automata Technology (QCA) in Computers and Communications Networks

Journal of Engineering and Applied Sciences, 2019-10, Vol.14 (1), p.8559-8568

2019

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Reduction of Power Dissipation in Logic Circuits

International journal of computer applications, 2011-01, Vol.24 (6), p.10-14

2011

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Implementation of MEMS Capacitive Pressure Sensor Design using COMSOL Software

International journal of recent technology and engineering, 2019-09, Vol.8 (2S8), p.967-972

2019

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Performance Analysis of Various Fin Patterns of Hybrid Tunnel FET

International Journal of Electrical and Electronics Research, 2022-12, Vol.10 (4), p.806-810

2022

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1.5mW,14.68V/µS-Low Power and High Speed Comparator Design for ADC Applications

International journal of innovative technology and exploring engineering, 2019-07, Vol.8 (6S4), p.1322-1326

2019

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WITHDRAWN: Outage analysis of half-duplex decode-and-forward relaying with cooperative NOMA in vehicular networks

Materials today : proceedings, 2021-02

2021

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WITHDRAWN: SS < 30 mV/dec; Hybrid tunnel FET 3D analytical model for IoT applications

Materials today : proceedings, 2020-11

2020

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High Performance and Low Leakage 3DSOI Fin-FET SRAM

American journal of engineering and applied sciences, 2017-01, Vol.10 (1), p.101-107

2017

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Design Of Area Efficent 32 Bit Arithmetic And Logic Unit (Alu) For Dsp Processors

International journal of engineering and advanced technology, 2019-11, Vol.8 (6s3), p.1270-1278

2019

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Compact Modeling of Capacitance Based 14 nm Triple Gate FinFET Using Verilog-A

Journal of computational and theoretical nanoscience, 2020-07, Vol.17 (9), p.4553-4558

2020

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3D Analytical Modeling Of Surface Potential And Threshold Voltage Model Of Dm Fintfet With Dual Hetero Gate Oxide Structure

Turkish journal of computer and mathematics education, 2021-04, Vol.12 (2), p.1245-1259

Et. al, Ajay kumar Dharmireddy

2021

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Analysis of Sub-threshold Inverter and 6T SRAM Cell for Ultra-Low-Power Applications

Intelligent Communication, Control and Devices, 2018, Vol.624, p.1401-1413

2018

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Design of Low Voltage-Power: Negative capacitance Charge Plasma FinTFET for AIOT Data Acquisition Blocks

2022 International Conference on Breakthrough in Heuristics And Reciprocation of Advanced Technologies (BHARAT), 2022, p.144-149

2022

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A Novel design of SOI based Fin Gate TFET

2021 2nd Global Conference for Advancement in Technology (GCAT), 2021, p.1-4

2021

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0.7V-20nm FinFET Technology Inverter Design for Better Log-Linear Characteristics

Intelligent Circuit and Systems for SDG3-Good Health and Well-Being, 2025, p.341-349

1, 2025

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IMPLEMENTATION OF LOW POWER AND LOW ENERGY SYNCHRONOUS SAPT LOGIC

International journal of distributed and parallel systems, 2012-01, Vol.3 (1), p.185-185

2012

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Next-Generation Connectivity: A Holistic Review of Cooperative NOMA in Dynamic Vehicular Networks for Intelligent Transportation Systems

Quantum-Dot Cellular Automata Technology for High-Speed High-Data-Rate Networks

A 75 μW Two-Stage Op-Amp using 0.18μW CMOS Technology for High-Speed Operations

SOI FinFET Based 10T SRAM Cell Design against Short Channel Effects

50mv/Bar Sensitivity; Piezoresistive MEMS Altimeter Design for The Agricultural Drones

Optimal Relay Selection Strategy for Efficient and Reliable Cluster-Based Cooperative Multi-Hop Transmission in Vehicular Communication

A 9-bit pseudo-noise-based calibrated successive approximation ADC with differential/integral nonlinearity enhancement

Design and analysis of high performance 9 bit SAR ADC with SFDR 76.59

Design of 14 bit current steering d/a converter with self-checking circuit for high speed iot applications

Aggressive Development of Qunatum-Dot Cellular Automata Technology (QCA) in Computers and Communications Networks

Reduction of Power Dissipation in Logic Circuits

Implementation of MEMS Capacitive Pressure Sensor Design using COMSOL Software

Performance Analysis of Various Fin Patterns of Hybrid Tunnel FET

1.5mW,14.68V/µS-Low Power and High Speed Comparator Design for ADC Applications

WITHDRAWN: Outage analysis of half-duplex decode-and-forward relaying with cooperative NOMA in vehicular networks

WITHDRAWN: SS < 30 mV/dec; Hybrid tunnel FET 3D analytical model for IoT applications

High Performance and Low Leakage 3DSOI Fin-FET SRAM

Design Of Area Efficent 32 Bit Arithmetic And Logic Unit (Alu) For Dsp Processors

Compact Modeling of Capacitance Based 14 nm Triple Gate FinFET Using Verilog-A

3D Analytical Modeling Of Surface Potential And Threshold Voltage Model Of Dm Fintfet With Dual Hetero Gate Oxide Structure

Analysis of Sub-threshold Inverter and 6T SRAM Cell for Ultra-Low-Power Applications

Design of Low Voltage-Power: Negative capacitance Charge Plasma FinTFET for AIOT Data Acquisition Blocks

A Novel design of SOI based Fin Gate TFET

0.7V-20nm FinFET Technology Inverter Design for Better Log-Linear Characteristics

IMPLEMENTATION OF LOW POWER AND LOW ENERGY SYNCHRONOUS SAPT LOGIC

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