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A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS

IEEE journal of solid-state circuits, 2020-06, Vol.55 (6), p.1553-1564

2020

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A 1024-Channel 268-nW/Pixel 36×36 μm2/Channel Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces

IEEE journal of solid-state circuits, 2024-04, Vol.59 (4), p.1123-1136

2024

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Multi-Gigahertz Nyquist Analog-To-Digital Converters: Architecture and Circuit Innovations in Deep-Scaled CMOS and FinFET Technologies

1, 2023

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A 13.5-Gb/s 5-mV-Sensitivity 26.8-ps-CLK-OUT Delay Triple-Latch Feedforward Dynamic Comparator in 28-nm CMOS

IEEE solid-state circuits letters, 2019-09, Vol.2 (9), p.167-170

2019

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A 13.5-Gb/s 5-mV-Sensitivity 26.8-ps-CLK-OUT Delay Triple-Latch Feedforward Dynamic Comparator in 28-nm CMOS

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019, p.167-170

2019

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A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS

IEEE journal of solid-state circuits, 2018-07, Vol.53 (7), p.1889-1901

2018

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A 28 nm CMOS Triple-Latch Feed-Forward Dynamic Comparator With <27 ps / 1 V and <70 ps / 0.6 V Delay at 5 mV-Sensitivity

IEEE transactions on circuits and systems. I, Regular papers, 2022-11, Vol.69 (11), p.4404-4414

2022

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A 28 nm CMOS Triple-Latch Feed-Forward Dynamic Comparator With <27 ps / 1 V and

IEEE transactions on circuits and systems. I, Regular papers, 2022-01, Vol.69 (11), p.4404

2022

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A 1024-Channel 268-nW/Pixel 36×36 μm 2 /Channel Data-Compressive Neural Recording IC for High-Bandwidth Brain–Computer Interfaces

IEEE journal of solid-state circuits, 2024-04, Vol.59 (4), p.1123-1136

2024

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Conclusions, Contributions, and Future Work

Multi-Gigahertz Nyquist Analog-to-Digital Converters, 2023, p.247-256

2023

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High-Resolution Wide-Bandwidth Time-Interleaved RF ADC

Multi-Gigahertz Nyquist Analog-to-Digital Converters, 2023, p.183-216

2023

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Ultra-Wideband Direct RF Receiver Analog Front-End

Multi-Gigahertz Nyquist Analog-to-Digital Converters, 2023, p.217-246

2023

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Architectural Considerations for High-Efficiency GHz-Range ADCs

Multi-Gigahertz Nyquist Analog-to-Digital Converters, 2023, p.57-120

2023

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Analog-to-Digital Conversion Fundamentals

Multi-Gigahertz Nyquist Analog-to-Digital Converters, 2023, p.15-56

2023

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Ultrahigh-Speed High-Sensitivity Dynamic Comparator

Multi-Gigahertz Nyquist Analog-to-Digital Converters, 2023, p.121-147

2023

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High-Speed Wide-Bandwidth Single-Channel SAR ADC

Multi-Gigahertz Nyquist Analog-to-Digital Converters, 2023, p.149-181

2023

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Introduction

Multi-Gigahertz Nyquist Analog-to-Digital Converters, 2022, p.1-13

2022

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An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

Electronics (Basel), 2019-01, Vol.8 (1), p.13

2019

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High-Linearity High-Bandwidth (>20GHz) T&H Front Ends Using Active Bootstrapping and Heterogeneous SiGe/CMOS Circuit Co-Design

2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023, p.1-5

2023

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Medusa: A 0.83/4.6 \mathrm/Frame 86/91.6%-CIFAR-10 TinyML Processor with Pipelined Pixel Streaming of Bottleneck Layers in 28nm CMOS

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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A 30GHz-BW < -57dB-IM3 Direct RF Receiver Analog Front End in 16nm FinFET

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, p.100-101

2022

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3.3 A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoMS in 28nm CMOS

2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, p.62-64

2019

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A 56 GS/s 8-bit 0.011 mm2 4x Delta-Interleaved Switched-Capacitor DAC in 16nm FinFET CMOS

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC), 2022, p.329-332

2022

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In the Pursuit of the Optimal Accuracy-Speed-Power Analog-to-Digital Converter Architecture: A mathematical framework

IEEE solid state circuits magazine, 2022, Vol.14 (1), p.45-53

2022

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A 36.4dB SNDR @ 5GHz 1.25GS/s 7b 3.56mW single-channel SAR ADC in 28nm bulk CMOS

ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, 2017, p.167-170

2017

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A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS

A 1024-Channel 268-nW/Pixel 36×36 μm2/Channel Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces

Multi-Gigahertz Nyquist Analog-To-Digital Converters: Architecture and Circuit Innovations in Deep-Scaled CMOS and FinFET Technologies

A 13.5-Gb/s 5-mV-Sensitivity 26.8-ps-CLK-OUT Delay Triple-Latch Feedforward Dynamic Comparator in 28-nm CMOS

A 13.5-Gb/s 5-mV-Sensitivity 26.8-ps-CLK-OUT Delay Triple-Latch Feedforward Dynamic Comparator in 28-nm CMOS

A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS

A 28 nm CMOS Triple-Latch Feed-Forward Dynamic Comparator With <27 ps / 1 V and <70 ps / 0.6 V Delay at 5 mV-Sensitivity

A 28 nm CMOS Triple-Latch Feed-Forward Dynamic Comparator With <27 ps / 1 V and

A 1024-Channel 268-nW/Pixel 36×36 μm 2 /Channel Data-Compressive Neural Recording IC for High-Bandwidth Brain–Computer Interfaces

Conclusions, Contributions, and Future Work

High-Resolution Wide-Bandwidth Time-Interleaved RF ADC

Ultra-Wideband Direct RF Receiver Analog Front-End

Architectural Considerations for High-Efficiency GHz-Range ADCs

Analog-to-Digital Conversion Fundamentals

Ultrahigh-Speed High-Sensitivity Dynamic Comparator

High-Speed Wide-Bandwidth Single-Channel SAR ADC

Introduction

An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

High-Linearity High-Bandwidth (>20GHz) T&H Front Ends Using Active Bootstrapping and Heterogeneous SiGe/CMOS Circuit Co-Design

Medusa: A 0.83/4.6 \mathrm/Frame 86/91.6%-CIFAR-10 TinyML Processor with Pipelined Pixel Streaming of Bottleneck Layers in 28nm CMOS

A 30GHz-BW < -57dB-IM3 Direct RF Receiver Analog Front End in 16nm FinFET

3.3 A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoMS in 28nm CMOS

A 56 GS/s 8-bit 0.011 mm2 4x Delta-Interleaved Switched-Capacitor DAC in 16nm FinFET CMOS

In the Pursuit of the Optimal Accuracy-Speed-Power Analog-to-Digital Converter Architecture: A mathematical framework

A 36.4dB SNDR @ 5GHz 1.25GS/s 7b 3.56mW single-channel SAR ADC in 28nm bulk CMOS

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