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Maintaining Symmetry between Convolutional Neural Network Accuracy and Performance on an Edge TPU with a Focus on Transfer Learning Adjustments

Symmetry (Basel), 2024-01, Vol.16 (1), p.91

2024

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Another dimension in integrated circuit trust

Journal of cryptographic engineering, 2018-11, Vol.8 (4), p.315-326

2018

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Resource-aware architecture design and implementation of hough transform for a real-time iris boundary detection system

IEEE transactions on consumer electronics, 2014-08, Vol.60 (3), p.485-492

2014

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Toward Thermal Imaging Analysis to Characterize Operations of Solid-State Drives via the Temperature Side-Channel

2022 56th Asilomar Conference on Signals, Systems, and Computers, 2022, p.153-157

2022

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Monitoring Device Current to Characterize Trim Operations of Solid-State Drives

IEEE transactions on information forensics and security, 2019-05, Vol.14 (5), p.1296-1306

2019

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Ransomware Classification Using Hardware Performance Counters on a Non-Virtualized System

IEEE access, 2024, Vol.12, p.63865-63884

2024

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Energy Efficient Iris Recognition With Graphics Processing Units

IEEE access, 2016, Vol.4, p.2831-2839

2016

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Classifying Proprietary Firmware on a Solid State Drive Using Idle State Current Draw Measurements

IEEE access, 2020, Vol.8, p.31869-31881

2020

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Replacement techniques for dynamic NUCA cache designs on CMPs

The Journal of supercomputing, 2013-05, Vol.64 (2), p.548-579

2013

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Comparing an FPGA to a Cell for an Image Processing Application

EURASIP journal on advances in signal processing, 2010-01, Vol.2010 (1), Article 764838

2010

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Case for a field-programmable gate array multicore hybrid machine for an image-processing application

Journal of electronic imaging, 2011-01, Vol.20 (1), p.13015

2011

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Architecture Design for Feature Extraction and Template Matching in a Real-Time Iris Recognition System

Electronics (Basel), 2021-02, Vol.10 (3), p.241

2021

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Detecting firmware modification on solid state drives via current draw analysis

Computers & security, 2021-03, Vol.102, p.102149, Article 102149

2021

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Parallelizing Iris Recognition

IEEE transactions on information forensics and security, 2009-12, Vol.4 (4), p.812-823

2009

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Face detection with a Viola–Jones based hybrid network

IET biometrics, 2017-05, Vol.6 (3), p.200-210

2017

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Real-time video surveillance on an embedded, programmable platform

Microprocessors and microsystems, 2013-08, Vol.37 (6-7), p.562-571

2013

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Use of synthetic data to test biometric algorithms

Journal of electronic imaging, 2016-07, Vol.25 (4), p.43023

2016

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Meeting points: using thread criticality to adapt multicore hardware to parallel regions

2008 International Conference on Parallel Architectures and Compilation Techniques (PACT), 2008, p.240-249

2008

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Comparing an FPGA to a Cell for an Image Processing Application

EURASIP journal on advances in signal processing, 2010-01, Vol.2010 (1), p.764838-764838

2010

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Iris recognition using the Ridge Energy Direction (RED) algorithm

2008 42nd Asilomar Conference on Signals, Systems and Computers, 2008, p.1219-1223

2008

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Toward Classification of Phase Change Memory and 3D NAND Flash SSDs Using Power-based Side-channel Analysis in the Time-domain

Proceedings of the 2022 International Symposium on Memory Systems, 2022, p.1-7

2022

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A Performance Analysis of Deep Neural Network Models on an Edge Tensor Processing Unit

2022 International Conference on Electrical, Computer and Energy Technologies (ICECET), 2022, p.1-6

2022

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Efficient architecture design for the AES-128 algorithm on embedded systems

Proceedings of the 17th ACM International Conference on Computing Frontiers, 2020, p.89-97

2020

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Iris template generation with parallel logic

2008 42nd Asilomar Conference on Signals, Systems and Computers, 2008, p.1872-1875

2008

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The Fuzzy Correlation between Code and Performance Predictability

37th International Symposium on Microarchitecture (MICRO-37'04), 2004, p.93-104

2004

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Maintaining Symmetry between Convolutional Neural Network Accuracy and Performance on an Edge TPU with a Focus on Transfer Learning Adjustments

Another dimension in integrated circuit trust

Resource-aware architecture design and implementation of hough transform for a real-time iris boundary detection system

Toward Thermal Imaging Analysis to Characterize Operations of Solid-State Drives via the Temperature Side-Channel

Monitoring Device Current to Characterize Trim Operations of Solid-State Drives

Ransomware Classification Using Hardware Performance Counters on a Non-Virtualized System

Energy Efficient Iris Recognition With Graphics Processing Units

Classifying Proprietary Firmware on a Solid State Drive Using Idle State Current Draw Measurements

Replacement techniques for dynamic NUCA cache designs on CMPs

Comparing an FPGA to a Cell for an Image Processing Application

Case for a field-programmable gate array multicore hybrid machine for an image-processing application

Architecture Design for Feature Extraction and Template Matching in a Real-Time Iris Recognition System

Detecting firmware modification on solid state drives via current draw analysis

Parallelizing Iris Recognition

Face detection with a Viola–Jones based hybrid network

Real-time video surveillance on an embedded, programmable platform

Use of synthetic data to test biometric algorithms

Meeting points: using thread criticality to adapt multicore hardware to parallel regions

Comparing an FPGA to a Cell for an Image Processing Application

Iris recognition using the Ridge Energy Direction (RED) algorithm

Toward Classification of Phase Change Memory and 3D NAND Flash SSDs Using Power-based Side-channel Analysis in the Time-domain

A Performance Analysis of Deep Neural Network Models on an Edge Tensor Processing Unit

Efficient architecture design for the AES-128 algorithm on embedded systems

Iris template generation with parallel logic

The Fuzzy Correlation between Code and Performance Predictability

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