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A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing

IEEE journal of solid-state circuits, 2008-04, Vol.43 (4), p.946-955

2008

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Challenges and future directions for the scaling of dynamic random-access memory (DRAM)

IBM journal of research and development, 2002-03, Vol.46 (2.3), p.187-212

2002

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Embedded memory considerations in SOI

2010 IEEE International SOI Conference (SOI), 2010, p.1-2

2010

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A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements

IEEE journal of solid-state circuits, 2012-01, Vol.47 (1), p.97-106

2012

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High Performance Nanosheet Technology Optimized for 77 K

2023 International Electron Devices Meeting (IEDM), 2023, p.1-4

2023

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A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements

2011 IEEE International Solid-State Circuits Conference, 2011, p.254-256

2011

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Properties of four-layer planar optical waveguides near cutoff

IEEE journal of quantum electronics, 1987-07, Vol.23 (7), p.1172-1179

1987

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Raman microprobe analysis of strain induced by patterned dielectric films of GaAlAs structures

IEEE journal of quantum electronics, 1989-05, Vol.25 (5), p.989-992

1989

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Length minimization in integrated optical circuits incorporating directional couplers and curved sections

Journal of lightwave technology, 1990-10, Vol.8 (10), p.1504-1508

1990

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Leakage current and reliability evaluation of ultra-thin reoxidized nitride and comparison with silicon dioxides

2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320), 2002, p.255-267

2002

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High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005, 2005, p.126-127

2005

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Fluctuation limits & scaling opportunities for CMOS SRAM cells

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest, 2005, p.659-662

2005

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1.5-V single work-function W/WN/n+-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

IEEE electron device letters, 2002-10, Vol.23 (10), p.621-623

2002

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J-R: Are Design Tools and Methodologies Measuring up to the Challenges of the DFM Era?

2007 IEEE Symposium on VLSI Technology, 2007, p.150-150

2007

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1.5-V single work-function W/WN/n super(+)-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

IEEE electron device letters, 2002-01, Vol.23 (10)

2002

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1.5-V single work-function W/WN/n(+)-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

IEEE electron device letters, 2002-10, Vol.23 (10), p.621-623

2002

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1.5-V single work-function W/WN/n/sup +/-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

IEEE electron device letters, 2002-10, Vol.23 (10), p.621-623

2002

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A 7F(2) cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs

IEEE journal of solid-state circuits, 2000-05, Vol.35 (5), p.713-718

2000

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Thickness and polarity dependence of intrinsic breakdown of ultra-thin reoxidized-nitride for DRAM technology applications

International Electron Devices Meeting. IEDM Technical Digest, 1997, p.77-80

1997

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Plasma immersion ion implantation as an alternative deep trench buried-plate doping technology

2000 International Conference on Ion Implantation Technology Proceedings. Ion Implantation Technology - 2000 (Cat. No.00EX432), 2000, p.460-463

2000

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A 7F/sup 2/ cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs

IEEE journal of solid-state circuits, 2000-05, Vol.35 (5), p.713-718

2000

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A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs

IEEE journal of solid-state circuits, 2000-05, Vol.35 (5), p.713

2000

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A 7F super(2) cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs

IEEE journal of solid-state circuits, 2000-01, Vol.35 (5)

2000

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High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization

2014 IEEE International Electron Devices Meeting, 2014, p.3.8.1-3.8.3

2014

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A lithographically-friendly 6F/sup 2/ DRAM cell

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517), 2001, p.97-100

2001

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A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing

Challenges and future directions for the scaling of dynamic random-access memory (DRAM)

Embedded memory considerations in SOI

A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements

High Performance Nanosheet Technology Optimized for 77 K

A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements

Properties of four-layer planar optical waveguides near cutoff

Raman microprobe analysis of strain induced by patterned dielectric films of GaAlAs structures

Length minimization in integrated optical circuits incorporating directional couplers and curved sections

Leakage current and reliability evaluation of ultra-thin reoxidized nitride and comparison with silicon dioxides

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

Fluctuation limits & scaling opportunities for CMOS SRAM cells

1.5-V single work-function W/WN/n+-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

J-R: Are Design Tools and Methodologies Measuring up to the Challenges of the DFM Era?

1.5-V single work-function W/WN/n super(+)-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

1.5-V single work-function W/WN/n(+)-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

1.5-V single work-function W/WN/n/sup +/-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

A 7F(2) cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs

Thickness and polarity dependence of intrinsic breakdown of ultra-thin reoxidized-nitride for DRAM technology applications

Plasma immersion ion implantation as an alternative deep trench buried-plate doping technology

A 7F/sup 2/ cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs

A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs

A 7F super(2) cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs

High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization

A lithographically-friendly 6F/sup 2/ DRAM cell

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