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A 2.4-GHz 20-40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS

IEEE journal of solid-state circuits, 2012-12, Vol.47 (12), p.3184-3196

2012

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A 2 GHz 244 fs-Resolution 1.2 ps-Peak-INL Edge Interpolator-Based Digital-to-Time Converter in 28 nm CMOS

IEEE journal of solid-state circuits, 2016-12, Vol.51 (12), p.2992-3004

2016

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802.11g/n Compliant Fully Integrated Wake-Up Receiver With −72-dBm Sensitivity in 14-nm FinFET CMOS

IEEE journal of solid-state circuits, 2018-05, Vol.53 (5), p.1411-1422

2018

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A Fully Integrated 27-dBm Dual-Band All-Digital Polar Transmitter Supporting 160 MHz for Wi-Fi 6 Applications

IEEE journal of solid-state circuits, 2020-12, Vol.55 (12), p.3414-3425

2020

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A Transformer-Combined 31.5 dBm Outphasing Power Amplifier in 45 nm LP CMOS With Dynamic Power Control for Back-Off Power Efficiency Enhancement

IEEE journal of solid-state circuits, 2012-07, Vol.47 (7), p.1646-1658

2012

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A Cellular Multiband DTC-Based Digital Polar Transmitter With −153-dBc/Hz Noise in 14-nm FinFET

IEEE journal of solid-state circuits, 2020-07, Vol.55 (7), p.1830-1841

2020

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A Flip-Chip-Packaged 25.3 dBm Class-D Outphasing Power Amplifier in 32 nm CMOS for WLAN Application

IEEE journal of solid-state circuits, 2011-07, Vol.46 (7), p.1596-1605

2011

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A Class-E PA With Pulse-Width and Pulse-Position Modulation in 65 nm CMOS

IEEE journal of solid-state circuits, 2009-06, Vol.44 (6), p.1668-1678

2009

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11.3 A 1.8W High-Frequency SIMO Converter Featuring Digital Sensor-Less Computational Zero-Current Operation and Non-Linear Duty-Boost

2023 IEEE International Solid- State Circuits Conference (ISSCC), 2023, p.10-12

2023

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A 39.1-to-41.6GHz ΔΣ Fractional-N Frequency Synthesizer in 90nm CMOS

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008, p.484-630

2008

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A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ Modulator Based on Standard Cell Design With Time-Interleaving

IEEE journal of solid-state circuits, 2010-07, Vol.45 (7), p.1410-1420

2010

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A 16nm, +28dBm Dual-Band All-Digital Polar Transmitter Based on 4-core Digital PA for Wi-Fi6E Applications

2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, Vol.65, p.324-326

2022

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A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique

IEEE journal of solid-state circuits, 2013-07, Vol.48 (7), p.1721-1729

2013

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32.6 A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS

2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, Vol.64, p.451-453

2021

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95µW 802.11g/n compliant fully-integrated wake-up receiver with −72dBm sensitivity in 14nm FinFET CMOS

2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2017, p.172-175

2017

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10.5 A Fully Integrated 27dBm Dual-Band All-Digital Polar Transmitter Supporting 160MHz for WiFi 6 Applications

2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, p.180-182

2020

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A 32nm, 0.65-10GHz, 0.9/0.3 ps/σ TX/RX jitter single inductor digital fractional-n clock generator for reconfigurable serial I/O

2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2017, p.1-6

2017

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A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver

IEEE journal of solid-state circuits, 2013-01, Vol.48 (1), p.91-103

2013

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A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, Delta capital sigma Modulator Based on Standard Cell Design With Time-Interleaving

IEEE journal of solid-state circuits, 2010-07, Vol.45 (7), p.1410-1420

2010

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A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, [Delta][Sigma] Modulator Based on Standard Cell Design With Time-Interleaving

IEEE journal of solid-state circuits, 2010-07, Vol.45 (7), p.1410

2010

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A highly linear 25dBm outphasing power amplifier in 32nm CMOS for WLAN application

2010 Proceedings of ESSCIRC, 2010, p.306-309

2010

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A 5-GHz 20-dBm Power Amplifier With Digitally Assisted AM-PM Correction in a 90-nm CMOS Process

IEEE journal of solid-state circuits, 2006-08, Vol.41 (8), p.1757-1763

2006

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A Flip-Chip-Packaged 25.3 dBm Class-D Outphasing Power Amplifier in 32 nm CMOS for WLAN Application: SPECIAL ISSUE ON THE 36th EUROPEAN SOLID-STATE CIRCUITS CONFERENCE (ESSCIRC)

IEEE journal of solid-state circuits, 2011, Vol.46 (7), p.1596-1605

2011

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2.9 A 2GHz 244fs-resolution 1.2ps-Peak-INL edge-interpolator-based digital-to-time converter in 28nm CMOS

2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016, p.52-54

2016

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A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management

2012 IEEE International Solid-State Circuits Conference, 2012, p.352-354

2012

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A 2.4-GHz 20-40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS

A 2 GHz 244 fs-Resolution 1.2 ps-Peak-INL Edge Interpolator-Based Digital-to-Time Converter in 28 nm CMOS

802.11g/n Compliant Fully Integrated Wake-Up Receiver With −72-dBm Sensitivity in 14-nm FinFET CMOS

A Fully Integrated 27-dBm Dual-Band All-Digital Polar Transmitter Supporting 160 MHz for Wi-Fi 6 Applications

A Transformer-Combined 31.5 dBm Outphasing Power Amplifier in 45 nm LP CMOS With Dynamic Power Control for Back-Off Power Efficiency Enhancement

A Cellular Multiband DTC-Based Digital Polar Transmitter With −153-dBc/Hz Noise in 14-nm FinFET

A Flip-Chip-Packaged 25.3 dBm Class-D Outphasing Power Amplifier in 32 nm CMOS for WLAN Application

A Class-E PA With Pulse-Width and Pulse-Position Modulation in 65 nm CMOS

11.3 A 1.8W High-Frequency SIMO Converter Featuring Digital Sensor-Less Computational Zero-Current Operation and Non-Linear Duty-Boost

A 39.1-to-41.6GHz ΔΣ Fractional-N Frequency Synthesizer in 90nm CMOS

A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ Modulator Based on Standard Cell Design With Time-Interleaving

A 16nm, +28dBm Dual-Band All-Digital Polar Transmitter Based on 4-core Digital PA for Wi-Fi6E Applications

A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique

32.6 A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS

95µW 802.11g/n compliant fully-integrated wake-up receiver with −72dBm sensitivity in 14nm FinFET CMOS

10.5 A Fully Integrated 27dBm Dual-Band All-Digital Polar Transmitter Supporting 160MHz for WiFi 6 Applications

A 32nm, 0.65-10GHz, 0.9/0.3 ps/σ TX/RX jitter single inductor digital fractional-n clock generator for reconfigurable serial I/O

A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver

A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, Delta capital sigma Modulator Based on Standard Cell Design With Time-Interleaving

A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, [Delta][Sigma] Modulator Based on Standard Cell Design With Time-Interleaving

A highly linear 25dBm outphasing power amplifier in 32nm CMOS for WLAN application

A 5-GHz 20-dBm Power Amplifier With Digitally Assisted AM-PM Correction in a 90-nm CMOS Process

A Flip-Chip-Packaged 25.3 dBm Class-D Outphasing Power Amplifier in 32 nm CMOS for WLAN Application: SPECIAL ISSUE ON THE 36th EUROPEAN SOLID-STATE CIRCUITS CONFERENCE (ESSCIRC)

2.9 A 2GHz 244fs-resolution 1.2ps-Peak-INL edge-interpolator-based digital-to-time converter in 28nm CMOS

A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management

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