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A sub-wavelength Si LED integrated in a CMOS platform

Nature communications, 2023-02, Vol.14 (1), p.882-882, Article 882

2023

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Engineering Breakdown Probability Profile for PDP and DCR Optimization in a SPAD Fabricated in a Standard 55 nm BCD Process

IEEE journal of selected topics in quantum electronics, 2022-03, Vol.28 (2: Optical Detectors), p.1-10

2022

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A 3.3-Gb/s SPAD-Based Quantum Random Number Generator

IEEE journal of solid-state circuits, 2023-09, Vol.58 (9), p.1-16

2023

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Enhanced second-harmonic generation in strained germanium-on-insulator microdisks for integrated quantum photonic technologies

Optics letters, 2023-08, Vol.48 (16), p.4269-4271

2023

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A Gradient-Gated SPAD Array for Non-Line-of-Sight Imaging

IEEE journal of selected topics in quantum electronics, 2024-01, Vol.30 (1: Single-Photon Technologies and Applications), p.1-10

2024

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Single-photon avalanche diode fabricated in standard 55 nm bipolar-CMOS-DMOS technology with sub-20 V breakdown voltage

Optics express, 2023-04, Vol.31 (9), p.13798-13805

2023

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Doping Engineering for PDP Optimization in SPADs Implemented in 55-nm BCD Process

IEEE journal of selected topics in quantum electronics, 2024-01, Vol.30 (1: Single-Photon Technologies and Applications), p.1-7

2024

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On Analog Silicon Photomultipliers in Standard 55-nm BCD Technology for LiDAR Applications

IEEE journal of selected topics in quantum electronics, 2022-09, Vol.28 (5: Lidars and Photonic Radars), p.1-10

2022

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Anomalous narrow width effect in p-channel metal–oxide–semiconductor surface channel transistors using shallow trench isolation technology

Microelectronics and reliability, 2008-06, Vol.48 (6), p.919-922

2008

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SPAD Developed in 55 nm Bipolar-CMOS-DMOS Technology Achieving Near 90% Peak PDP

IEEE journal of selected topics in quantum electronics, 2024-01, Vol.30 (1: Single-Photon Technologies and Applications), p.1-10

2024

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A Modular Three-Dimensional Hall Effect Sensor for Performance Optimization

IEEE sensors journal, 2022-06, Vol.22 (12), p.1-1

2022

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Enhanced Hot-Hole Induced Degradation of Strained p-Channel Metal Oxide Semiconductor Transistors in Complementary Metal Oxide Semiconductor Technology with 2.0 nm Gate Oxide

Japanese Journal of Applied Physics, 2005-08, Vol.44 (8R), p.5953

2005

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Effective Channel Length Shortening and Mobility Increase of p-Channel Metal Oxide Semiconductor Transistors Resulting in Higher Drive Current Using Short Source–Drain Diffusion Length

Japanese Journal of Applied Physics, 2004, Vol.43 (3R), p.925-930

2004

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First Foundry Three-Dimensional Hall Effect Sensor for System-on-Chip Integration

2020 IEEE Sensors, 2020, p.1-3

2020

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High Performance Device Design through Parasitic Junction Capacitance Reduction and Junction Leakage Current Suppression beyond 0.1 µm Technology

Japanese Journal of Applied Physics, 2003-04, Vol.42 (Part 1, No. 4B), p.2144-2148

2003

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Reduced Hot-Carrier Induced Degradation of NMOS I/O Transistors with Sub-micron Source-Drain Diffusion Length for 0.11 µm Dual Gate Oxide CMOS Technology

Japanese Journal of Applied Physics, 2005-04, Vol.44 (4S), p.2125

2005

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Low-power and high-sensitivity system-on-chip hall effect sensor

2017 IEEE SENSORS, 2017, p.1-3

2017

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Enhancing leakage suppression in carbon-rich silicon junctions

IEEE electron device letters, 2006-06, Vol.27 (6), p.442-444

2006

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Defect suppression of indium end-of-range during solid phase epitaxy annealing using Si 1− y C y in silicon

Thin solid films, 2006, Vol.504 (1), p.132-135

2006

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Influence of substitutional carbon incorporation on implanted-indium-related defects and transient enhanced diffusion

Applied physics letters, 2003-11, Vol.83 (20), p.4169-4171

2003

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Leakage suppression of gated diodes fabricated under low-temperature annealing with substitutional carbon Si1-yCy incorporation

IEEE electron device letters, 2005-04, Vol.26 (4), p.252-254

2005

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Gesn Bonding Technology for Integrated Laser-on-Chip Photonics

Meeting abstracts (Electrochemical Society), 2022-10, Vol.MA2022-02 (32), p.1177-1177

2022

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Defect suppression of indium end-of-range during solid phase epitaxy annealing using Si1-yCy in silicon

Thin solid films, 2006-05, Vol.504 (1-2), p.132-135

2006

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Anomalous Narrow Width Effect in NMOS and PMOS Surface Channel Transistors Using Shallow Trench Isolation

2005 IEEE Conference on Electron Devices and Solid-State Circuits, 2005, p.773-776

2005

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Tunnel DCIV diagnosis of ultrathin gate oxide metal-oxide-silicon transistors

Semiconductor science and technology, 2004-07, Vol.19 (7), p.870-876

2004

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A sub-wavelength Si LED integrated in a CMOS platform

Engineering Breakdown Probability Profile for PDP and DCR Optimization in a SPAD Fabricated in a Standard 55 nm BCD Process

A 3.3-Gb/s SPAD-Based Quantum Random Number Generator

Enhanced second-harmonic generation in strained germanium-on-insulator microdisks for integrated quantum photonic technologies

A Gradient-Gated SPAD Array for Non-Line-of-Sight Imaging

Single-photon avalanche diode fabricated in standard 55 nm bipolar-CMOS-DMOS technology with sub-20 V breakdown voltage

Doping Engineering for PDP Optimization in SPADs Implemented in 55-nm BCD Process

On Analog Silicon Photomultipliers in Standard 55-nm BCD Technology for LiDAR Applications

Anomalous narrow width effect in p-channel metal–oxide–semiconductor surface channel transistors using shallow trench isolation technology

SPAD Developed in 55 nm Bipolar-CMOS-DMOS Technology Achieving Near 90% Peak PDP

A Modular Three-Dimensional Hall Effect Sensor for Performance Optimization

Enhanced Hot-Hole Induced Degradation of Strained p-Channel Metal Oxide Semiconductor Transistors in Complementary Metal Oxide Semiconductor Technology with 2.0 nm Gate Oxide

Effective Channel Length Shortening and Mobility Increase of p-Channel Metal Oxide Semiconductor Transistors Resulting in Higher Drive Current Using Short Source–Drain Diffusion Length

First Foundry Three-Dimensional Hall Effect Sensor for System-on-Chip Integration

High Performance Device Design through Parasitic Junction Capacitance Reduction and Junction Leakage Current Suppression beyond 0.1 µm Technology

Reduced Hot-Carrier Induced Degradation of NMOS I/O Transistors with Sub-micron Source-Drain Diffusion Length for 0.11 µm Dual Gate Oxide CMOS Technology

Low-power and high-sensitivity system-on-chip hall effect sensor

Enhancing leakage suppression in carbon-rich silicon junctions

Defect suppression of indium end-of-range during solid phase epitaxy annealing using Si 1− y C y in silicon

Influence of substitutional carbon incorporation on implanted-indium-related defects and transient enhanced diffusion

Leakage suppression of gated diodes fabricated under low-temperature annealing with substitutional carbon Si1-yCy incorporation

Gesn Bonding Technology for Integrated Laser-on-Chip Photonics

Defect suppression of indium end-of-range during solid phase epitaxy annealing using Si1-yCy in silicon

Anomalous Narrow Width Effect in NMOS and PMOS Surface Channel Transistors Using Shallow Trench Isolation

Tunnel DCIV diagnosis of ultrathin gate oxide metal-oxide-silicon transistors

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