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Dynamic Reference Voltage Sensing Scheme for Read Margin Improvement in STT-MRAMs

IEEE transactions on circuits and systems. I, Regular papers, 2018-04, Vol.65 (4), p.1269-1278

2018

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Time-Based Sensing for Reference-Less and Robust Read in STT-MRAM Memories

IEEE transactions on circuits and systems. I, Regular papers, 2018-10, Vol.65 (10), p.3338-3348

2018

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A low‐power charge‐based integrate‐and‐fire circuit for binarized‐spiking neural network

International journal of circuit theory and applications, 2023-07, Vol.51 (7), p.3404-3414

2023

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STT-BSNN: An In-Memory Deep Binary Spiking Neural Network Based on STT-MRAM

IEEE access, 2021, Vol.9, p.151373-151385

2021

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FeCBF: A Novel Sub-Optimal Cascaded Bloom Filter Structure Based on Feature Extraction

IEEE access, 2024, Vol.12, p.67619-67631

2024

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A LUT-based scheme for LNA linearization in direct RF sampling receivers

Physical communication, 2022-02, Vol.50, p.101530, Article 101530

2022

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STT-MRAM Architecture with Parallel Accumulator for In-Memory Binary Neural Networks

2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, p.1-5

2021

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An Accurate and Compact Hyperbolic Tangent and Sigmoid Computation Based Stochastic Logic

2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2021, p.386-390

2021

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A Novel In-memory Matching Circuit Based on Non-volatile Resistive Memory

2022 International Conference on IC Design and Technology (ICICDT), 2022, p.97-100

2022

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Sub-optimal Deep Pipelined Implementation of MIMO Sphere Detector on FPGA

EAI endorsed transactions on industrial networks and intelligent systems, 2023-03, Vol.10 (1), p.e3

2023

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Novel Time-Based Sensing Scheme for STT-MRAMs

2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, p.1-5

2018

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Novel Boosted-Voltage Sensing Scheme for Variation-Resilient STT-MRAM Read

IEEE transactions on circuits and systems. I, Regular papers, 2016-10, Vol.63 (10), p.1652-1660

2016

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STT-BNN: A Novel STT-MRAM In-Memory Computing Macro for Binary Neural Networks

IEEE journal on emerging and selected topics in circuits and systems, 2022-06, Vol.12 (2), p.1-1

2022

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NUTS-BSNN: A non-uniform time-step binarized spiking neural network with energy-efficient in-memory computing macro

Neurocomputing (Amsterdam), 2023-12, Vol.560, p.126838, Article 126838

2023

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Voltage Scaled STT-MRAMs Towards Minimum-Energy Write Access

IEEE journal on emerging and selected topics in circuits and systems, 2016-09, Vol.6 (3), p.305-318

2016

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A robust Euclidean metric based ID extraction method using RO-PUFs in FPGA

Integration (Amsterdam), 2022-01, Vol.82, p.37-47

2022

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A Low-Cost Dual-Band RF Power Amplifier for Wireless Communication Systems

Radioengineering, 2023-04, Vol.32 (1), p.136-141

2023

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LNA linearization solution for direct conversion receiver using under-sampling technique in reference receiver

Physical communication, 2023-08, Vol.59, p.102059, Article 102059

2023

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FBW-SNN: A Fully Binarized Weights-Spiking Neural Networks for Edge-AI Applications

2022 International Conference on IC Design and Technology (ICICDT), 2022, p.105-108

2022

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XNOR-BSNN: In-Memory Computing Model for Deep Binarized Spiking Neural Network

2021 International Conference on High Performance Big Data and Intelligent Systems (HPBD&IS), 2021, p.17-21

2021

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Methods and Techniques for Increasing the Accuracy of Continuous Non-invasive Blood Pressure Measurement Under Dynamic Loads

Proceedings of International Scientific Conference on Telecommunications, Computing and Control, 2021, Vol.220, p.141-151

2021

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An Effective Design Approach to Implementation of MIMO-SDM-PNC Relay Stations on FPGA

2022 11th International Conference on Control, Automation and Information Sciences (ICCAIS), 2022, p.358-363

2022

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A Bufferless Non-exact Matching Hardware Accelerator for Processing Large Non-uniform Stream Data

Industrial Networks and Intelligent Systems, p.245-258

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Modeling the impact of dynamic voltage scaling on 1T-1J STT-RAM write energy and performance

2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, p.2313-2316

2015

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Enhanced ID Authentication Scheme Using FPGA-Based Ring Oscillator PUF

2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), 2019, p.320-327

2019

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Dynamic Reference Voltage Sensing Scheme for Read Margin Improvement in STT-MRAMs

Time-Based Sensing for Reference-Less and Robust Read in STT-MRAM Memories

A low‐power charge‐based integrate‐and‐fire circuit for binarized‐spiking neural network

STT-BSNN: An In-Memory Deep Binary Spiking Neural Network Based on STT-MRAM

FeCBF: A Novel Sub-Optimal Cascaded Bloom Filter Structure Based on Feature Extraction

A LUT-based scheme for LNA linearization in direct RF sampling receivers

STT-MRAM Architecture with Parallel Accumulator for In-Memory Binary Neural Networks

An Accurate and Compact Hyperbolic Tangent and Sigmoid Computation Based Stochastic Logic

A Novel In-memory Matching Circuit Based on Non-volatile Resistive Memory

Sub-optimal Deep Pipelined Implementation of MIMO Sphere Detector on FPGA

Novel Time-Based Sensing Scheme for STT-MRAMs

Novel Boosted-Voltage Sensing Scheme for Variation-Resilient STT-MRAM Read

STT-BNN: A Novel STT-MRAM In-Memory Computing Macro for Binary Neural Networks

NUTS-BSNN: A non-uniform time-step binarized spiking neural network with energy-efficient in-memory computing macro

Voltage Scaled STT-MRAMs Towards Minimum-Energy Write Access

A robust Euclidean metric based ID extraction method using RO-PUFs in FPGA

A Low-Cost Dual-Band RF Power Amplifier for Wireless Communication Systems

LNA linearization solution for direct conversion receiver using under-sampling technique in reference receiver

FBW-SNN: A Fully Binarized Weights-Spiking Neural Networks for Edge-AI Applications

XNOR-BSNN: In-Memory Computing Model for Deep Binarized Spiking Neural Network

Methods and Techniques for Increasing the Accuracy of Continuous Non-invasive Blood Pressure Measurement Under Dynamic Loads

An Effective Design Approach to Implementation of MIMO-SDM-PNC Relay Stations on FPGA

A Bufferless Non-exact Matching Hardware Accelerator for Processing Large Non-uniform Stream Data

Modeling the impact of dynamic voltage scaling on 1T-1J STT-RAM write energy and performance

Enhanced ID Authentication Scheme Using FPGA-Based Ring Oscillator PUF

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