UB Paderborn / Katalog / Suche / in CDI

Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers

IEEE transactions on very large scale integration (VLSI) systems, 2008-06, Vol.16 (6), p.639-649

2008

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Discrete-time battery models for system-level low-power design

IEEE transactions on very large scale integration (VLSI) systems, 2001-10, Vol.9 (5), p.630-640

2001

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SystemC cosimulation and emulation of multiprocessor SoC designs

Computer (Long Beach, Calif.), 2003-04, Vol.36 (4), p.53-59

2003

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Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits

IEEE transactions on circuits and systems. I, Regular papers, 2009-09, Vol.56 (9), p.1979-1993

2009

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On-chip process variation-tracking through an all-digital monitoring architecture

IET circuits, devices & systems, 2012-09, Vol.6 (5), p.366-366

2012

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Fast Computation of Discharge Current Upper Bounds for Clustered Power Gating

IEEE transactions on very large scale integration (VLSI) systems, 2011-01, Vol.19 (1), p.146-151

2011

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Tag Overflow Buffering: Reducing Total Memory Energy by Reduced-Tag Matching

IEEE transactions on very large scale integration (VLSI) systems, 2009-05, Vol.17 (5), p.728-732

2009

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Discharge current steering for battery lifetime optimization

IEEE transactions on computers, 2003-08, Vol.52 (8), p.985-995

2003

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Layout-driven memory synthesis for embedded systems-on-chip

IEEE transactions on very large scale integration (VLSI) systems, 2002-04, Vol.10 (2), p.96-105

2002

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Design Techniques and Architectures for Low-Leakage SRAMs

IEEE transactions on circuits and systems. I, Regular papers, 2012-09, Vol.59 (9), p.1992-2007

2012

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Low-energy RGB color approximation for digital LCD interfaces

IEEE transactions on consumer electronics, 2006-08, Vol.52 (3), p.1004-1012

2006

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Architectures and synthesis algorithms for power-efficient bus interfaces

IEEE transactions on computer-aided design of integrated circuits and systems, 2000-09, Vol.19 (9), p.969-980

2000

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Enabling concurrent clock and power gating in an industrial design flow

2009 Design, Automation & Test in Europe Conference & Exhibition, 2009, p.334-339

2009

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SystemC-AMS Thermal Modeling for the Co-simulation of Functional and Extra-Functional Properties

ACM transactions on design automation of electronic systems, 2019-01, Vol.24 (1), p.1-26

2019

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Synthesis of application-specific memories for power optimization in embedded systems

Annual ACM IEEE Design Automation Conference: Proceedings of the 37th conference on Design automation; 05-09 June 2000, 2000, p.300-303

2000

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Energy-efficient bus encoding for LCD digital display interfaces

IEEE transactions on consumer electronics, 2005-05, Vol.51 (2), p.624-634

2005

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Scheduling battery usage in mobile systems

IEEE transactions on very large scale integration (VLSI) systems, 2003-12, Vol.11 (6), p.1136-1143

2003

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Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 2006, p.214-224

2006

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Design Techniques for NBTI-Tolerant Power-Gating Architectures

IEEE transactions on circuits and systems. II, Express briefs, 2012-04, Vol.59 (4), p.249-253

2012

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Power optimization of core-based systems by address bus encoding

IEEE transactions on very large scale integration (VLSI) systems, 1998-12, Vol.6 (4), p.554-562

1998

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Timing-driven row-based power gating

International Symposium on Low Power Electronics and Design: Proceedings of the 2007 international symposium on Low power electronics and design; 27-29 Aug. 2007, 2007, p.104-109

2007

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Parameterized RTL power models for soft macros

IEEE transactions on very large scale integration (VLSI) systems, 2001-12, Vol.9 (6), p.880-887

2001

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Wire placement for crosstalk energy minimization in address buses

Design, Automation, and Test in Europe: Proceedings of the conference on Design, automation and test in Europe; 04-08 Mar. 2002, 2002, p.158-162

2002

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Energy-aware design techniques for differential power analysis protection

Annual ACM IEEE Design Automation Conference: Proceedings of the 40th conference on Design automation; 02-06 June 2003, 2003, p.36-41

2003

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Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers

ACM transactions on design automation of electronic systems, 1999-10, Vol.4 (4), p.351-375

1999

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Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers

Discrete-time battery models for system-level low-power design

SystemC cosimulation and emulation of multiprocessor SoC designs

Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits

On-chip process variation-tracking through an all-digital monitoring architecture

Fast Computation of Discharge Current Upper Bounds for Clustered Power Gating

Tag Overflow Buffering: Reducing Total Memory Energy by Reduced-Tag Matching

Discharge current steering for battery lifetime optimization

Layout-driven memory synthesis for embedded systems-on-chip

Design Techniques and Architectures for Low-Leakage SRAMs

Low-energy RGB color approximation for digital LCD interfaces

Architectures and synthesis algorithms for power-efficient bus interfaces

Enabling concurrent clock and power gating in an industrial design flow

SystemC-AMS Thermal Modeling for the Co-simulation of Functional and Extra-Functional Properties

Synthesis of application-specific memories for power optimization in embedded systems

Energy-efficient bus encoding for LCD digital display interfaces

Scheduling battery usage in mobile systems

Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective

Design Techniques for NBTI-Tolerant Power-Gating Architectures

Power optimization of core-based systems by address bus encoding

Timing-driven row-based power gating

Parameterized RTL power models for soft macros

Wire placement for crosstalk energy minimization in address buses

Energy-aware design techniques for differential power analysis protection

Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers

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