UB Paderborn / Katalog / Suche / in CDI

Sortiert nach

Einfacher Volltextzugriff von (fast) überall

Installieren Sie die LibKey Nomad-Browsererweiterung und erhalten Sie von vielen Webseiten einfachen Zugriff auf lizenzierte Volltexte oder Open Access Publikationen. Mehr erfahren...

Longest Path Selection Based on Path Identifiers

IEEE access, 2024, Vol.12, p.14512-14520

Pomeranz, Irith

2024

Volltextzugriff (PDF)

Sharing of Topped-Off Compressed Test Sets Among Logic Blocks

IEEE access, 2024-01, Vol.12, p.1-1

Pomeranz, Irith

2024

Volltextzugriff (PDF)

Functional Compaction for Functional Test Sequences

IEEE access, 2024, Vol.12, p.98130-98140

Pomeranz, Irith

2024

Volltextzugriff (PDF)

Storage and Counter Based Logic Built-In Self-Test

IEEE access, 2023, Vol.11, p.139335-139344

Pomeranz, Irith

2023

Volltextzugriff (PDF)

Low-Power Diagnostic Test Sets for Transition Faults Based on Functional Broadside Tests

IEEE transactions on very large scale integration (VLSI) systems, 2014-11, Vol.22 (11), p.2428-2432

Pomeranz, Irith

2014

Volltextzugriff (PDF)

Enhanced Test Compaction for Multicycle Broadside Tests by Using State Complementation

ACM transactions on design automation of electronic systems, 2015-12, Vol.21 (1), p.1-20

Pomeranz, Irith

2015

Volltextzugriff (PDF)

Design-for-testability for multi-cycle broadside tests by holding of state variables

ACM transactions on design automation of electronic systems, 2014-03, Vol.19 (2), p.1-20

Pomeranz, Irith

2014

Volltextzugriff (PDF)

Test Insertion for Dynamic Test Compaction

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-04, Vol.43 (4), p.1302-1306

Pomeranz, Irith

2024

Volltextzugriff (PDF)

Dynamic Test Compaction of a Compressed Test Set Shared Among Logic Blocks

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-01, Vol.43 (1), p.1-1

Pomeranz, Irith

2024

Volltextzugriff (PDF)

Test Generation for Functionally-Possible Subpaths

IEEE transactions on computer-aided design of integrated circuits and systems, 2024, p.1-1

Pomeranz, Irith

2024

Volltextzugriff (PDF)

Unconstrained-Activation Functional-Detection Scan-Based Tests

IEEE transactions on computer-aided design of integrated circuits and systems, 2024, p.1-1

Pomeranz, Irith

2024

Volltextzugriff (PDF)

Functional Design-for-Testability for Functional Test Sequences

IEEE transactions on computer-aided design of integrated circuits and systems, 2024, p.1-1

Pomeranz, Irith

2024

Volltextzugriff (PDF)

Partially Specified Output Response for Reduced Fail Data Volume

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-09, Vol.42 (9), p.3123-3127

Pomeranz, Irith

2023

Volltextzugriff (PDF)

Bit-Complemented Test Data to Replace the Tail of a Fault Coverage Curve

IEEE transactions on very large scale integration (VLSI) systems, 2024-04, Vol.32 (4), p.609-618

Pomeranz, Irith

2024

Volltextzugriff (PDF)

Storage-Based Logic Built-In Self-Test With Partitioned Deterministic Compressed Tests

IEEE transactions on very large scale integration (VLSI) systems, 2023-09, Vol.31 (9), p.1-10

Pomeranz, Irith

2023

Volltextzugriff (PDF)

Storage-Based Logic Built-In Self-Test With Cyclic Tests

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-09, Vol.42 (9), p.3118-3122

Pomeranz, Irith

2023

Volltextzugriff (PDF)

Testability Evaluation for Local Design Modifications

IEEE transactions on very large scale integration (VLSI) systems, 2024-01, Vol.32 (1), p.195-199

Pomeranz, Irith

2024

Volltextzugriff (PDF)

Estimating the Number of Extra Tests During Iterative Test Generation for Single-Cycle Gate-Exhaustive Faults

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-08, Vol.42 (8), p.2752-2760

Pomeranz, Irith

2023

Volltextzugriff (PDF)

Maximal Independent Fault Set for Gate-Exhaustive Faults

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-03, Vol.40 (3), p.598-602

Pomeranz, Irith

2021

Volltextzugriff (PDF)

Dummy Faulty Units for Reduced Fail Data Volume From Logic Faults

IEEE transactions on very large scale integration (VLSI) systems, 2023-11, Vol.31 (11), p.1-9

Pomeranz, Irith

2023

Volltextzugriff (PDF)

Storage-Based Built-In Self-Test for Gate-Exhaustive Faults

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-10, Vol.40 (10), p.2189-2193

Pomeranz, Irith

2021

Volltextzugriff (PDF)

Functionally Possible Scan-Based Test Set as a Dual of a Compressed Multicycle Test Set

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-04, Vol.42 (4), p.1336-1345

Pomeranz, Irith

2023

Volltextzugriff (PDF)

Sharing of Compressed Tests Among Logic Blocks

IEEE transactions on very large scale integration (VLSI) systems, 2023-04, Vol.31 (4), p.421-430

Pomeranz, Irith

2023

Volltextzugriff (PDF)

Topping Off Test Sets Under Bounded Transparent Scan

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-01, Vol.42 (1), p.341-345

Pomeranz, Irith

2023

Volltextzugriff (PDF)

GEPDFs: Path Delay Faults Based on Two-Cycle Gate-Exhaustive Faults

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-07, Vol.41 (7), p.2315-2322

Pomeranz, Irith

2022

Volltextzugriff (PDF)

1 – 25 von 677

Suche als RSS-Feed

Suchergebnisse filtern

Filter anzeigen

Nur zeigen

Geprüft (Peer-Review)
(307)
Mit Volltextzugriff
(665)

Publikationsform

Sprache

Englisch
(677)
Japanisch
(4)

Erscheinungsjahr

n.n

Thema

Science & Technology
(534)
Technology
(534)
Computer Science
(494)
Circuit Faults
(467)
Engineering
(455)
Engineering, Electrical & Electronic
(455)
Computer Science, Hardware & Architecture
(445)
Circuit Testing
(287)
Fault Detection
(285)
Electrical Fault Detection
(171)
Cities And Towns
(167)
Clocks
(147)
Compaction
(147)
Test Generation
(136)
Benchmark Testing
(133)
Computer Science, Interdisciplinary Applications
(127)
Faults
(127)
Fault Diagnosis
(123)
Transition Faults
(116)
Circuits
(114)

15 weitere anzeigen...

Weniger anzeigen...

Neu hinzugefügt

Menü

Weitere Dienste

Einstellungen

Longest Path Selection Based on Path Identifiers

Sharing of Topped-Off Compressed Test Sets Among Logic Blocks

Functional Compaction for Functional Test Sequences

Storage and Counter Based Logic Built-In Self-Test

Low-Power Diagnostic Test Sets for Transition Faults Based on Functional Broadside Tests

Enhanced Test Compaction for Multicycle Broadside Tests by Using State Complementation

Design-for-testability for multi-cycle broadside tests by holding of state variables

Test Insertion for Dynamic Test Compaction

Dynamic Test Compaction of a Compressed Test Set Shared Among Logic Blocks

Test Generation for Functionally-Possible Subpaths

Unconstrained-Activation Functional-Detection Scan-Based Tests

Functional Design-for-Testability for Functional Test Sequences

Partially Specified Output Response for Reduced Fail Data Volume

Bit-Complemented Test Data to Replace the Tail of a Fault Coverage Curve

Storage-Based Logic Built-In Self-Test With Partitioned Deterministic Compressed Tests

Storage-Based Logic Built-In Self-Test With Cyclic Tests

Testability Evaluation for Local Design Modifications

Estimating the Number of Extra Tests During Iterative Test Generation for Single-Cycle Gate-Exhaustive Faults

Maximal Independent Fault Set for Gate-Exhaustive Faults

Dummy Faulty Units for Reduced Fail Data Volume From Logic Faults

Storage-Based Built-In Self-Test for Gate-Exhaustive Faults

Functionally Possible Scan-Based Test Set as a Dual of a Compressed Multicycle Test Set

Sharing of Compressed Tests Among Logic Blocks

Topping Off Test Sets Under Bounded Transparent Scan

GEPDFs: Path Delay Faults Based on Two-Cycle Gate-Exhaustive Faults

Suchergebnisse filtern