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Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation 10th International Workshop,PATMOS 2000 Göttingen, Germany, September 13–15, 2000 Proceedings

2000

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Hardware-Abbildung eines videobasierten Verfahrens zur echtzeitfähigen Auswertung von Winkelhistogrammen auf eine modulare Coprozessor-Architektur

Advances in radio science, 2010-10, Vol.8, p.135-142

2010

Volltextzugriff (PDF)

VLSI Implementations for Image Communications

Pirsch, P

1, 1993

Volltextzugriff (PDF)

VLSI architectures for video compression-a survey

Proceedings of the IEEE, 1995-02, Vol.83 (2), p.220-246

1995

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EVALUATION OF PENALTY FUNCTIONS FOR SEMI-GLOBAL MATCHING COST AGGREGATION

International archives of the photogrammetry, remote sensing and spatial information sciences., 2012-07, Vol.XXXIX-B3, p.1-6

2012

Volltextzugriff (PDF)

VLSI Implementations for Image Communications

Pirsch, P

2014

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Multicore system-on-chip architecture for MPEG-4 streaming video

IEEE transactions on circuits and systems for video technology, 2002-08, Vol.12 (8), p.688-699

2002

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VLSI implementations of image and video multimedia processing systems

IEEE transactions on circuits and systems for video technology, 1998-11, Vol.8 (7), p.878-891

1998

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Hardware-Abbildung eines videobasierten Verfahrens zur echtzeitfähigen Auswertung von Winkelhistogrammen auf eine modulare Coprozessor-Architektur

Advances in radio science, 2010-10, Vol.8, p.135-142

2010

Volltextzugriff (PDF)

Advances in picture coding

Proceedings of the IEEE, 1985-01, Vol.73 (4), p.523-548

1985

Volltextzugriff (PDF)

A 1.3-GOPS parallel DSP for high-performance image-processing applications

IEEE journal of solid-state circuits, 2000-07, Vol.35 (7), p.946-952

2000

Volltextzugriff (PDF)

Synthetic aperture radar with backprojection: A scalable, platform independent architecture for exhaustive FPGA resource utilization

2014 International Radar Conference, 2014, p.1-5

2014

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Development and potential of real-time FPGA frequency-based SAR image processing for short-range FMCW applications

2013 International Conference on Radar, 2013, p.101-105

2013

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A flexible real-time SAR processing platform for high resolution airborne image generation

Proceedings of 2011 IEEE CIE International Conference on Radar, 2011, Vol.1, p.26-29

2011

Volltextzugriff (PDF)

Implementation of pipelined multipliers on Xilinx FPGAs

Field-Programmable Logic and Applications, 2005, p.51-60

2005

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An SoC with two multimedia DSPs and a RISC core for video compression applications

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519), 2004, p.330-531 Vol.1

First edition, 2004

Volltextzugriff (PDF)

A video signal processor for MIMD multiprocessing

Annual ACM IEEE Design Automation Conference: Proceedings of the 35th annual conference on Design automation; 15-19 June 1998, 1998, p.50-55

1998

Volltextzugriff (PDF)

HiBRID-SoC: a multi-core system-on-chip architecture for multimedia signal processing applications

2003 Design, Automation and Test in Europe Conference and Exhibition, 2003, p.8-13 suppl.

2003

Volltextzugriff (PDF)

Multiprocessor performance for real-time processing of video coding applications

IEEE transactions on circuits and systems for video technology, 1992-06, Vol.2 (2), p.221-230

1992

Volltextzugriff (PDF)

Realization of a programmable parallel DSP for high performance image processing applications

Annual ACM IEEE Design Automation Conference: Proceedings of the 35th annual conference on Design automation; 15-19 June 1998, 1998, p.56-61

1998

Volltextzugriff (PDF)

Processor Architectures for Multimedia Applications

Embedded Processor Design Challenges, 2002, p.188-206

2002

Volltextzugriff (PDF)

Design of a DPCM codec for VLSI realization in CMOS technology

Proceedings of the IEEE, 1985-01, Vol.73 (4), p.592-598

Pirsch, P.

1985

Volltextzugriff (PDF)

Implementation of a multiprocessor system with distributed embedded DRAM on a large area integrated circuit

Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2000, p.105-113

2000

Volltextzugriff (PDF)

Architectures for multimedia signal processing

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461), 1999, p.1-12

Pirsch, P.

1999

Volltextzugriff (PDF)

VLSI chip set for 2D HDTV subband filtering with on-chip line memories

IEEE journal of solid-state circuits, 1993-12, Vol.28 (12), p.1354-1361

1993

Volltextzugriff (PDF)

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Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation 10th International Workshop,PATMOS 2000 Göttingen, Germany, September 13–15, 2000 Proceedings

Hardware-Abbildung eines videobasierten Verfahrens zur echtzeitfähigen Auswertung von Winkelhistogrammen auf eine modulare Coprozessor-Architektur

VLSI Implementations for Image Communications

VLSI architectures for video compression-a survey

EVALUATION OF PENALTY FUNCTIONS FOR SEMI-GLOBAL MATCHING COST AGGREGATION

VLSI Implementations for Image Communications

Multicore system-on-chip architecture for MPEG-4 streaming video

VLSI implementations of image and video multimedia processing systems

Hardware-Abbildung eines videobasierten Verfahrens zur echtzeitfähigen Auswertung von Winkelhistogrammen auf eine modulare Coprozessor-Architektur

Advances in picture coding

A 1.3-GOPS parallel DSP for high-performance image-processing applications

Synthetic aperture radar with backprojection: A scalable, platform independent architecture for exhaustive FPGA resource utilization

Development and potential of real-time FPGA frequency-based SAR image processing for short-range FMCW applications

A flexible real-time SAR processing platform for high resolution airborne image generation

Implementation of pipelined multipliers on Xilinx FPGAs

An SoC with two multimedia DSPs and a RISC core for video compression applications

A video signal processor for MIMD multiprocessing

HiBRID-SoC: a multi-core system-on-chip architecture for multimedia signal processing applications

Multiprocessor performance for real-time processing of video coding applications

Realization of a programmable parallel DSP for high performance image processing applications

Processor Architectures for Multimedia Applications

Design of a DPCM codec for VLSI realization in CMOS technology

Implementation of a multiprocessor system with distributed embedded DRAM on a large area integrated circuit

Architectures for multimedia signal processing

VLSI chip set for 2D HDTV subband filtering with on-chip line memories

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